Search

US-12618680-B2 - Package on package memory interface and configuration with error code correction

US12618680B2US 12618680 B2US12618680 B2US 12618680B2US-12618680-B2

Abstract

Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

Inventors

  • Rahul Gulati
  • Aishwarya Dubey
  • Nainala Vyagrheswarudu
  • Vasant Easwaran
  • Prashant Dinkar Karandikar
  • Mihir Mody

Assignees

  • TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date
20260505
Application Date
20230425
Priority Date
20140207

Claims (20)

  1. 1 . A circuit comprising: first and second data ports; a data bus configured to carry data, the data bus coupled to the first data port; an error code correction (ECC) bus configured to carry ECC bits associated with the data carried in the data bus; and a multiplexer having a first input coupled to the data bus, a second input coupled to the ECC bus, and an output coupled to the second data port.
  2. 2 . The circuit of claim 1 , further comprising an AND gate having an output coupled to a selection input of the multiplexer.
  3. 3 . The circuit of claim 2 , wherein the multiplexer is configured to select the first input when the selection input is high, and the second input when the selection input is low.
  4. 4 . The circuit of claim 1 , further comprising: a first memory having a third data port coupled to the first data port; and a second memory having a fourth data port coupled to the second data port.
  5. 5 . The circuit of claim 4 , further comprising: an ECC data port coupled to the ECC bus; and a fourth memory having a fifth data port coupled to the ECC data port.
  6. 6 . The circuit of claim 1 , further comprising a first memory having a third data port coupled to the first data port, and a fourth data port coupled to the second data port.
  7. 7 . The circuit of claim 6 , further comprising: an ECC data port coupled to the ECC bus; and a second memory having a fifth data port coupled to the ECC data port.
  8. 8 . The circuit of claim 7 , further comprising sixth and seventh data ports coupled to the data bus, wherein the first memory comprises eighth and ninth data ports respectively coupled to the sixth and seventh data ports.
  9. 9 . The circuit of claim 1 , wherein the data bus is a 32-bit bus, and wherein the ECC bus is an 8-bit bus.
  10. 10 . A device comprising a package comprising: a first die comprising: first and second data ports, a data bus configured to carry data, the data bus coupled to the first data port, an error code correction (ECC) bus configured to carry ECC bits associated with the data carried in the data bus, and a multiplexer having a first input coupled to the data bus, a second input coupled to the ECC bus, and an output coupled to the second data port; and a second die comprising: first and second data ports respectively coupled to the first and second data ports of the first die, and a memory coupled to the first and second data ports.
  11. 11 . The device of claim 10 , wherein the package comprises a ball grid array (BGA), wherein the first die is disposed between the BGA and the second die.
  12. 12 . The device of claim 10 , wherein the first die comprises a processor, and wherein the memory is configured to provide electronic storage to the processor.
  13. 13 . The device of claim 10 , wherein the first die comprises a third data port coupled to the data bus, wherein the third data port is unconnected to the second die.
  14. 14 . The device of claim 10 , wherein the first die comprises a third data port coupled to the ECC bus, wherein the third data port is unconnected to the second die.
  15. 15 . The device of claim 10 , wherein the memory is a double data rate memory.
  16. 16 . The device of claim 15 , wherein the memory is a low power double data rate 2 (LPDDR2) or low power double data rate 3 (LPDDR3) memory.
  17. 17 . The device of claim 10 , wherein the first and second data ports are 8-bit data ports.
  18. 18 . The device of claim 10 , wherein the multiplexer is dynamically selectable based on an address of the memory.
  19. 19 . The device of claim 18 , wherein the multiplexer is configured to provide data at the output of the multiplexer from the ECC bus for a first region of the memory, and provide data from the data bus at the output of the multiplexer for a second region of the memory, wherein, the first region is configured to store 16-bit data and the second region is configured to store 32-bit data.
  20. 20 . The device of claim 10 , wherein the memory does not include dedicated ECC pins.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 16/983,437, filed Aug. 3, 2020, which is a continuation of U.S. patent application Ser. No. 16/114,419, filed Aug. 28, 2018 (now U.S. Pat. No. 10,767,998), which is a continuation of U.S. patent application Ser. No. 14/587,878 filed Dec. 31, 2014 (now U.S. Pat. No. 10,089,172), which claims priority to India Provisional patent Application 583/CHE/2014, entitled “ENSURING DATA INTEGRITY FOR POP MEMORY USAGE IN FUNCTIONAL SAFETY CRITICAL APPLICATIONS WITH ASIL COMPLIANCE NEEDS,” and filed Feb. 7, 2014, which applications are incorporated by reference. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT Not Applicable. BACKGROUND OF THE INVENTION The preferred embodiments relate to circuits with package on package (PoP) memory interfaces, as well as configurations including the PoP memory interface and coupled memory. By way of background, FIG. 1 illustrates a cross-sectional side view of an integrated circuit PoP designated generally at 10. The configuration as shown in FIG. 1 is consistent with the prior art, but notably the preferred embodiments also are suitable for implementing in a same configuration, albeit with greater functionality and benefits as detailed later. By way of general introduction to both the prior art and the related packaging considerations of the preferred embodiments, therefore, PoP 10 has two or more integrated circuit packages 20 and 30 (also known as chips) stacked relative to one another, typically for saving space to serve application requirements where area or volume is constrained. For example, automobile applications in confined areas of a vehicle may call for PoP devices, as may other consumer devices, such as cell phones and cameras. In general, the overall dimensions of integrated circuit PoP, shown generally two dimensionally D1 by D2, but understood to include a third dimension D3 perpendicular to D1 and D2, typically occupy one cubic inch, or less. Each device 20 and 30 includes at least one functional die 22 and 32, respectively, atop a respective substrate 24 and 34. The two (or more) stacked PoP devices 20 and 30 may serve comparable functions such as multiple memories, or in a mixed logic-memory stacking the devices may differ, such as having a System-On-A-Chip (SoC) processor as the lower device, with memory stacked on top of the SoC processor and providing electronic storage to the processor. Each functional die 22 and 32 is encapsulated in a respective cover 26 and 36. Each package 20 and 30 has a respective set of connectors, typically by way of a ball grid array (BGA) 28 and 38. BGA 28 allows electrical connections between packages 20 and 30, while BGA 38 allows connections between package 30 and additional lines, such as are typically on a printed circuit board (PCB). In any event, the stacked arrangement of the PoP configuration reduces the two-dimensional space needed as compared to arranging the two chips separately in a generally same two dimensional plane. Other PoP advantages include shorter track length in the connections between the stacked devices, thereby improving performance, such as increasing speed and noise resistance. While PoP configurations are increasingly useful and provide benefits as described above, it has been observed in connection with the preferred embodiments that PoP configurations may provide limitations. Specifically, because of the confined volume created by PoP stacking, typically the number of pin connections between the stacked devices is limited, due to the layout of die on each stacked device and the stacked perimeter, as typically occupied by the BGA. One manner observed in which such pin limitations arises is the lack of support for data checking by memories manufactured for PoP applications. More particularly, as technology advances, there again arises a need for smaller devices where PoP might appear usable, but at the same time some environments and applications also are increasing the use of so-called “mission critical” data. For example, in contemporary automotive applications, data that formerly was not mission critical is evolving toward mission critical, as may be guided by manufacturer requirements or regulations, such as via Automotive Safety Integrity Level (ASIL). Consider the instance of video data for a vehicle backup camera; such data in some applications may not by itself be mission critical when used solely to depict an image to a vehicle operator, but as such data becomes used for vehicle control, such as controlling brakes, steering, or acceleration, the criticality of the data is considerably increased. Such mission critical data, by definition, requires assurances of greater if not absolute accuracy. In PCB layouts, some accuracy is sometimes achieved through the use of a single parity bit per byte (or other quantum) of data, or for greater accuracy, error code correction (ECC) bi