US-12618721-B2 - Capacitor-based temperature-sensing device

US12618721B2US 12618721 B2US12618721 B2US 12618721B2US-12618721-B2

Abstract

A temperature-sensing device configured to monitor a temperature is disclosed. The temperature-sensing device includes: a first capacitor comprising a first oxide layer with a first thickness; a second capacitor comprising a second oxide layer with a second thickness, wherein the second thickness of the second oxide layer is different from the first thickness of the first oxide layer; and a control logic circuit, coupled to the first and second capacitors, and configured to determine whether the monitored temperature is equal to or greater than a threshold temperature based on whether at least one of the first and second oxide layers breaks down.

Inventors

Shih-Lien Linus Lu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230809

Claims (20)

1 . A device configured to monitor a temperature, comprising: a first capacitor comprising a first oxide layer; a second capacitor comprising a second oxide layer, wherein the first oxide layer is associated with a first breakdown temperature when the first capacitor is biased under a first voltage, and the second oxide layer is associated with a second breakdown temperature when the second capacitor is biased under the first voltage; and a control logic circuit, coupled to the first and second capacitors, and configured to determine whether the monitored temperature is equal to or greater than a threshold temperature based on whether at least one of the first and second oxide layers breaks down.
2 . The device of claim 1 , wherein the first and second oxide layers are each coupled between respective metal contacts and semiconductor substrates.
3 . The device of claim 1 , wherein: the control logic circuit is coupled to the first and second capacitors through a first comparator circuit and a second comparator circuit, respectively; the first comparator circuit is coupled to the first capacitor and configured to compare a first current flowing through the first capacitor with a reference current; and the second comparator circuit is coupled to the second capacitor and configured to compare a second current flowing through the second capacitor with the reference current.
4 . The device of claim 3 , wherein the first oxide layer has a first thickness and the second oxide layer has a second thickness, where the second thickness is different from the first thickness.
5 . The device of claim 3 , wherein the threshold temperature is between the first and second breakdown temperatures.
6 . The device of claim 3 , wherein when the monitored temperature is higher than the first breakdown temperature but lower than the second breakdown temperature, the first oxide layer breaks down and the second oxide layer does not break down when both the first and second capacitors are biased under the first voltage.
7 . The device of claim 3 , wherein the first current becomes substantially higher than the reference current causing the first comparator circuit to output a first logic state, and the second current remains substantially lower than the reference current causing the second comparator circuit to output a second logic state logically inverted to the first logic state.
8 . The device of claim 7 , wherein the control logic circuit uses the first and second logic states to determine that the monitored temperature is higher than the first breakdown temperature but lower than the second breakdown temperature.
9 . The device of claim 3 , wherein when the first and second capacitors are to be biased under a second voltage substantially lower than the first voltage, the first current becomes substantially lower than the reference current and the second current remains substantially lower than the reference current.
10 . A device, comprising: a first capacitor comprising a first oxide layer; a second capacitor comprising a second oxide layer, wherein the first and second oxide layers have different breakdown temperatures; a control logic circuit, coupled to the first and second capacitors, and configured to estimate a temperature based on whether the temperature is greater than or equal to one of the breakdown temperatures of the first and second oxide layers.
11 . The device of claim 10 , wherein the first and second oxide layers are each coupled between respective metal contacts and semiconductor substrates.
12 . The device of claim 10 , wherein: the control logic circuit is coupled to the first and second capacitors through a first comparator circuit and a second comparator circuit, respectively; the first comparator circuit is coupled to the first capacitor and configured to compare a first current flowing through the first capacitor with a reference current; and the second comparator circuit is coupled to the second capacitor and configured to compare a second current flowing through the second capacitor with the reference current.
13 . The device of claim 12 , wherein when the temperature is higher than the breakdown temperature of the first oxide layer but lower than the breakdown temperature of the second oxide layer, the first oxide layer breaks down and the second oxide layer remains intact when both the first and second capacitors are biased under a first voltage.
14 . The device of claim 13 , wherein a first thickness of the first oxide layer is thicker than a second thickness of the second oxide layer.
15 . The device of claim 13 , wherein the first current becomes substantially higher than the reference current causing the first comparator circuit to output a first logic state, and the second current remains substantially lower than the reference current causing the second comparator circuit to output a second logic state logically inverted to the first logic state.
16 . The device of claim 15 , wherein the control logic circuit uses the first and second logic states to determine that the monitored temperature is higher than the breakdown temperature of the first oxide layer but lower than the breakdown temperature of the second oxide layer.
17 . The device of claim 13 , wherein when the first and second capacitors are to be biased under a second voltage substantially lower than the first voltage, the first current becomes substantially lower than the reference current and the second current remains substantially lower than the reference current.
18 . The device of claim 10 , wherein the first oxide layer has a first thickness and the second oxide layer has a second thickness, the device further comprising: a third capacitor comprising a third oxide layer with a third thickness, wherein the third thickness is different from the first and second thicknesses thereby causing the third oxide layer to have a different breakdown temperature from the respective breakdown temperatures of the first and second oxide layers, wherein the control logic circuit is further configured to monitor the temperature based on whether the temperature has become not lower than the breakdown temperatures of the first and second oxide layers but lower than the breakdown temperature of the third oxide layer thereby causing the first and second oxide layers to break down.
19 . A method, comprising: providing a plurality of capacitors, wherein each of the plurality of capacitors comprises: a respective metal contact, a respective semiconductor substrate, and a respective oxide layer that is associated with a respective breakdown temperature; applying a common voltage to the metal contacts in the plurality of capacitors to cause respective currents to flow through the plurality of capacitors; comparing each of the respective currents with a reference current so as to provide a respective logic state based on the respective breakdown temperature; and determining the environmental temperature using the respective logic state.
20 . The method of claim 19 , wherein each respective oxide layer has a respective thickness and is coupled between a respective metal contact and a respective semiconductor substrate.

Description

CROSS-REFERENCE TO RELATION APPLICATIONS This application is a continuation of U.S. patent Ser. No. 17/317,741, filed May 11, 2021, which is a continuation of U.S. patent application Ser. No. 16/041,141, filed on Jul. 20, 2018, now U.S. Pat. No. 11,009,404, which claims priority to U.S. Provisional Patent Application No. 62/564,715, filed on Sep. 28, 2017, each of which is incorporated by reference herein in their entireties. BACKGROUND Aggressive technology scaling for high performance integrated circuits has resulted in higher current densities in interconnection lines and devices, which in turn increases power dissipation. Generally, a significant amount of such dissipated power converts to heat, which thus causes a substantial rise in heat density. Respective different operation modes of each of the functional blocks in a high performance integrated circuit cause temperature gradients on a respective substrate where the integrated circuit is formed. The above-mentioned scenarios lead to a need for a lightweight, robust, and power-efficient on-chip temperature-sensing device that can be used for accurate thermal mapping and thermal management. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various features are not necessarily drawn to scale. In fact, the dimensions and geometries of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a block diagram of a temperature-sensing device, in accordance with some embodiments. FIG. 2 illustrates an exemplary circuit diagram of part of the temperature-sensing device of FIG. 1, in accordance with some embodiments. FIG. 3 illustrates a flow chart of an exemplary method to operate the temperature-sensing device of FIG. 1, in accordance with some embodiments. FIG. 4 illustrates soft breakdown behaviors of first and second MOS capacitors of the temperature-sensing device of FIG. 1 over various different temperatures, respectively, in accordance with some embodiments. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. To accurately monitor temperature of an integrated circuit, a variety of on-chip temperature-sensing devices have been proposed over the years such as, for example, an on-chip thermal sensor. In general, an on-chip thermal sensor is an integral part of an integrated circuit that provides one or more additional layers of protection. The on-chip thermal sensor can be used to detect whether the integrated circuit is being hacked, for example, by sensing a presence of an abnormal temperature. As such, the integrated circuit's security protection can be improved. The on-chip thermal sensor can also be used to provide feedback to other on-chip circuits/components so as to allow those on-chip circuits/components to adjust respective circuit parameter(s) to prevent generating excessive heat. Accordingly, the whole integrated circuit (system) can operate more efficiently and reliably. Conventional on-chip thermal sensors typically utilize a variety of temperature-varying physical parameters (e.g., voltage) to detect/measure temperature. Such conventional thermal sensors are subjected to a variety of issues when integrated into an integrated circuit. In an example, one or more diodes (p-n junction devices) are used to measure temperatur