US-12618870-B2 - Vertical probe card

US12618870B2US 12618870 B2US12618870 B2US 12618870B2US-12618870-B2

Abstract

Proposed is a vertical probe card capable of effectively testing the electrical characteristics of a test object without a body thereof being elastically bent or curved in a convex shape in the horizontal direction by pressure applied to opposite ends thereof.

Inventors

Bum Mo Ahn
Seung Ho Park
Sung Hyun BYUN

Assignees

POINT ENGINEERING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20220729
Priority Date: 20210830

Claims (11)

1 . A vertical probe card that is used in a test process of testing a chip manufactured on a wafer during a semiconductor manufacturing process and is capable of coping with a narrower pitch, the vertical probe card comprising: a space transformer having a connection pad; a guide plate provided under the space transformer so as to be spaced apart from the space transformer; and a probe pin inserted and installed into a hole of the guide plate, wherein the probe pin comprises: a first plunger located at an upper portion thereof and configured to be connected to the connection pad of the space transformer; a second plunger located at a lower portion thereof and configured to be connected to the chip; and an elastic portion configured to elastically displace the first plunger and the second plunger in a length direction of the probe pin, wherein the elastic portion has a uniform cross-sectional shape in a thickness direction of the probe pin, and the elastic portion has a uniform thickness in a width direction and the length direction of the probe pin, wherein the elastic portion is formed by repeatedly bending a plate, and an actual width of the plate and a thickness of the plate have a ratio in a range of 1:5 to 1:30.
2 . The vertical probe card of claim 1 , wherein a support portion configured to guide the elastic portion to be compressed and extended in the length direction of the probe pin and configured to prevent the elastic portion from being buckled when compressed is provided outside the elastic portion along the length direction of the probe pin.
3 . The vertical probe card of claim 2 , wherein the second plunger moves vertically upward inside the support portion and performs a wiping operation at a second contact point.
4 . The vertical probe card of claim 2 , wherein during an overdrive process in which the probe pin tests the chip, the support portion maintains a vertical state, and the second plunger performs a wiping operation on the chip as the second plunger is tilted while maintaining a contact pressure with the chip.
5 . The vertical probe card of claim 2 , wherein as the first plunger is vertically moved downward inside the support portion, an additional contact point is formed between the first plunger and the support portion.
6 . The vertical probe card of claim 2 , wherein the elastic portion comprises: a first elastic portion connected to the first plunger; a second elastic portion connected to the second plunger; and an intermediate fixing portion provided between the first elastic portion and the second elastic portion and provided integrally with the support portion.
7 . The vertical probe card of claim 6 , wherein before the probe pin tests the chip, the first plunger is in a state in contact with the connection pad so that the first elastic portion is compressively deformed in the length direction of the probe pin, and the second plunger is in a state not in contact with the chip, and when the probe pin tests the chip, the second plunger is brought into contact with the chip so that the second elastic portion is compressively deformed.
8 . The vertical probe card of claim 1 , wherein the vertical probe card tests a non-memory semiconductor chip.
9 . The vertical probe card of claim 1 , wherein a pitch between adjacent probe pins is in a range of 50 μm to 160 μm.
10 . The vertical probe card of claim 1 , wherein a lateral width of the probe pin is in a range of 40 μm to 200 μm, and a thickness of the probe pin is in a range of 40 μm to 200 μm.
11 . A vertical probe card that is used in a test process of testing a chip manufactured on a wafer during a semiconductor manufacturing process and is capable of coping with a narrower pitch, the vertical probe card comprising: a space transformer having a connection pad; a guide plate provided under the space transformer so as to be spaced apart from the space transformer; and a probe pin inserted and installed into a hole of the guide plate, wherein the probe pin comprises: a first plunger located at an upper portion thereof and configured to be connected to the connection pad of the space transformer; a second plunger located at a lower portion thereof and configured to be connected to the chip; and an elastic portion configured to elastically displace the first plunger and the second plunger in a length direction of the probe pin, wherein the elastic portion has a uniform cross-sectional shape in a thickness direction of the probe pin, and the elastic portion has a uniform thickness in a width direction and the length direction of the probe pin, wherein a plurality of fine trenches are formed in a side surface of the probe pin in a corrugated shape in which peaks and valleys with a depth in a range of 20 nm to 1 μm are repeated along the side surface of the probe pin in a direction orthogonal to the thickness direction of the probe pin.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a 371 of international application of PCT application serial no. PCT/KR2022/011156, filed on Jul. 29, 2022, which claims the priority benefit of Korea application no. 10-2021-0114423, filed on Aug. 30, 2021. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. TECHNICAL FIELD The present disclosure relates to a vertical probe card. BACKGROUND ART FIG. 1 is a view schematically illustrating a vertical probe card 1 according to the related art, and FIGS. 2 and 3 are enlarged views illustrating a probe head 4 illustrated in FIG. 1. The testing of semiconductor chips at the wafer-level is performed by a probe card. The probe card is mounted between a wafer and a head of test equipment. About 8,000 to 100,000 probe pins on the probe card are brought into contact with pads in individual chips on the wafer to play the role of an intermediate medium that allows test signals to be exchanged between probe equipment and the individual chips. The types of the probe card may be classified into a vertical probe card, a cantilever probe card, and a micro-electro-mechanical system (MEMS) probe card. The present disclosure relates to the vertical probe card among these probe cards. The vertical probe card 1 generally includes a circuit board 2, a space transformer 3 provided under the circuit board 2, and a probe head 4 provided under the space transformer 3. The probe head 4 includes a plurality of probe pins 7 and guide plates 5 and 6 having guide holes into which the probe pins 7 are inserted. The probe head 4 includes an upper guide plate 5 and a lower guide plate 6. The upper guide plate 5 and the lower guide plate 6 are fixedly installed through a spacer. The probe pins 7 have a structure elastically deformable between the upper guide plate 5 and the lower guide plate 6, and these probe pins 7 are adopted to constitute the vertical probe card 1. Referring to FIGS. 2 and 3, a test for electrical characteristics of a semiconductor device is performed by approaching a wafer W to the probe card 1 having the plurality of probe pins 7 and then bringing the respective probe pins 7 into contact with corresponding electrode pads WP on the wafer W. After the probe pins 7 reach positions where the probe pins 7 are brought into contact with the electrode pads WP, an overdrive process is performed to further lift the wafer W by a predetermined height toward the probe card 1. The overdrive process is inevitable because there is a difference in length between the plurality of probe pins 7 due to errors in a manufacturing process, and there is a slight difference in flatness between the guide plates 5 and 6 and the space transformer 3, and there is a difference in height between the electrode pads WP. During the overdrive process, an oxide layer 8 formed on each electrode pad WP is removed and each probe pin 7 and a conductive material layer of the electrode pad WP are electrically connected to each other, whereby the electrical characteristics of the semiconductor device are tested. In order to ensure good electrical and mechanical contact for all the probe pins 7, an overdrive with sufficient upward stroke is required. Consequently, a greater pressing force than a certain level is required to provide a sufficient overdrive for the plurality of probe pins 7. However, this high pressing force causes the probe pins 7 to apply excessive pressure to inner walls of the guide holes of the guide plates 5 and 6. Such excessive pressure results in abrasion of the inner walls of the guide holes, generating foreign substances. These foreign substances fall to the electrode pads WP, thereby making it difficult to test electrical characteristics. In addition, since the overdrive process is repeated with excessive pressure, fatigue failure of the probe pins 7 occurs in a short period of time. Meanwhile, referring to FIG. 4, the oxide layer 8 removed by the probe pin 7 generates shavings. When the probe pin 7 is buckled, i.e., bent or curved, by the pressure applied to opposite ends of the probe pin 7, the contact point of the probe pin 7 removes the oxide layer 8 under a high contact pressure, and this excessive contact pressure results in formation of a large concave on the surface of the electrode pad WP. Such a large concave causes a poor connection in a bonding process of the semiconductor device, and excessively generated shavings adhere to the ends of the probe pin 7, thereby increasing contact resistance. Meanwhile, the probe pins 7 used in the related-art vertical probe card 1 are inserted into the upper and lower guide plates 5 and 6 and are buckled in one direction by the pressure applied to the opposite ends thereof while being supported by the guide plates 5 and 6. With the recent trend in semiconductor devices toward the integration of multiple functions in one device and faster proce