US-12618896-B2 - Active thermal interposer device with thermal isolation structures

US12618896B2US 12618896 B2US12618896 B2US 12618896B2US-12618896-B2

Abstract

An active thermal interposer (ATI) device for use in testing integrated circuit device under test (DUT) having thermal isolation structures. The ATI device includes a formation having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the formation, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the formation is disposed adjacent to an interface surface of the DUT during testing of the DUT. The ATI device includes a plurality of thermal resistance structures configured to resist thermal conductance between the plurality of heating zones.

Inventors

Karthik Ranganathan
Todd Berk
Ian Williams
Mohammad Ghazvini
Thomas Jones
Aritomo Kikuchi
Merlin Wallner
Rajan SURVE
Samer Kabbani
Paul Ferrari
Ikeda Hiroki
Kiyokawa Toshiyuki
Gregory Cruzan

Assignees

ADVANTEST TEST SOLUTIONS, INC.

Dates

Publication Date: 20260505
Application Date: 20240213

Claims (20)

1 . An active thermal interposer (ATI) device for testing a device under test (DUT), said ATI device comprising: a formation comprising one or more layers, said formation comprising: a first thermal zone; and a second thermal zone; said first thermal zone configured to apply thermal energy to a first thermal region of said DUT, and wherein said DUT is an integrated circuit device; said second thermal zone configured to apply thermal energy to a second thermal region of said DUT, wherein said second thermal zone is configured to control a temperature of said second thermal region of said DUT independently of a temperature of said first thermal region of said DUT, wherein further said first thermal zone is configured to control said temperature of said first thermal region of said DUT independently of said temperature of said second thermal region of said DUT; and a thermal resistance structure, disposed in said formation and located between said first thermal zone and said second thermal zone, said thermal resistance structure configured to limit conductance of thermal energy therebetween.
2 . The ATI device of claim 1 wherein said thermal resistance structure comprises a trench formed in said formation and located between said first thermal zone and said second thermal zone.
3 . The ATI device of claim 2 wherein said trench is formed through all layers of said formation.
4 . The ATI device of claim 2 wherein said trench is formed through fewer than all layers of said formation.
5 . The ATI device of claim 1 further comprising an EMI shield layer.
6 . The ATI device of claim 1 wherein said thermal resistance structure comprises a portion raised above a surface of said formation.
7 . The ATI device of claim 6 wherein said thermal resistance structure comprises a same material as a surface of said formation.
8 . The ATI device of claim 1 wherein said thermal resistance structure comprises a plurality of substantially similar holes formed in said formation.
9 . The ATI device of claim 8 further comprising an EMI shield layer comprising conductive elements disposed in areas between said plurality of substantially similar holes.
10 . A testing device for testing an integrated circuit device under test (DUT), said testing device comprising: a stand-alone active thermal interposer device for use in testing said DUT and for coupling with a thermal controller, said stand-alone active thermal interposer device comprising: a body layer having a first surface and a second surface, wherein said first surface is operable to be disposed adjacent to a cold plate; and a plurality of heating zones defined across a second surface of said body layer, said plurality of heating zones operable to be controlled by said thermal controller to selectively heat and maintain respective temperatures thereof, said plurality of heating zones operable to heat a plurality of areas of said DUT when said second surface of said body layer is disposed adjacent to an interface surface of said DUT during said testing of said DUT; and a plurality of thermal resistance structures formed in said body layer and operable to resist thermal conductance between the plurality of heating zones.
11 . The testing device of claim 10 further comprising a thermal head for coupling to the thermal controller and operable to interface with said stand-alone active thermal interposer device during said testing of said DUT, said thermal head comprising: said cold plate; and an insulation cover for insulating said cold plate, wherein said insulation cover comprises an injection port for reducing condensation from said cold plate.
12 . The testing device of claim 10 wherein said plurality of thermal resistance structures comprises a plurality of trenches formed in said body layer and located between said plurality of heating zones.
13 . The testing device of claim 10 wherein said plurality of thermal resistance structures comprises portions raised above a surface of said body layer.
14 . The testing device of claim 13 wherein said plurality of thermal resistance structures comprises a same material as said body layer.
15 . The testing device of claim 10 wherein said plurality of thermal resistance structures comprises a plurality of substantially similar holes formed in said body layer.
16 . The testing device of claim 10 further comprising a system of cooling to remove heat from said cold plate.
17 . The testing device of claim 10 further comprising a thermal interface material layer disposed between said stand-alone active thermal interposer device and said cold plate for coupling thermal energy from said stand-alone active thermal interposer device to said cold plate.
18 . The testing device of claim 10 wherein said plurality of heating zones comprise resistive heaters.
19 . A testing arrangement for testing an integrated circuit device under test (DUT), said testing arrangement comprising: a socket device for containing said DUT and for interfacing with a load board; a stand-alone active thermal interposer device for use in testing said DUT, said stand-alone active thermal interposer device comprising: a body layer having a first surface and a second surface, wherein said first surface is operable to be disposed adjacent to a cold plate; and a plurality of heating zones defined across a second surface of said body layer, said plurality of heating zones operable to be controlled to selectively heat and maintain respective temperatures thereof, said plurality of heating zones operable to heat a plurality of areas of the DUT when said stand-alone active thermal interposer device is inserted into said socket device and said second surface of said body layer is disposed adjacent to an interface surface of said DUT; and wherein said body layer comprises a plurality of thermal resistance structures configured to resist thermal conductance between the plurality of heating zones.
20 . The testing arrangement of claim 19 further comprising: a thermal head operable to interface with said stand-alone active thermal interposer device during said testing of said DUT, said thermal head comprising said cold plate; and a thermal controller for coupling with said stand-alone active thermal interposer device to control said plurality of heating zones and to control said cold plate, said thermal controller comprising firmware operable to perform thermal regulation during testing of said DUT.

Description

RELATED APPLICATION(S) This Application is a Continuation in Part of, and claims priority to co-pending, commonly-owned U.S. application Ser. No. 18/204,309, filed May 31, 2023, entitled “Active Thermal Interposer Device,” to Kabbani et al., which in turn was a Continuation of U.S. application Ser. No. 17/841,471, now U.S. Pat. No. 11,846,669, filed Jun. 15, 2022, entitled “Active Thermal Interposer Device,” which in turn was a Continuation of U.S. application Ser. No. 17/531,638, now U.S. Pat. No. 11,609,266, filed Nov. 19, 2021, entitled “Active Thermal Interposer Device,” which in turn claimed priority to U.S. Provisional Application Ser. No. 63/121,532, filed Dec. 4, 2020, entitled “Active Thermal Interposer.” This application is related to U.S. Pat. No. 9,291,667 filed Mar. 4, 2014, entitled “Adaptive Thermal Control,” Ser. No. 14/196,955. This application is related to U.S. Pat. No. 11,567,119, filed Nov. 19, 2021, entitled “Testing System Including Active Thermal Interposer Device,” Ser. No. 17/531,649 and related to U.S. Pat. No. 11,754,620, filed May 13, 2022, entitled “DUT Placement and Handling for Active Thermal Interposer Device,” Ser. No. 17/744,403 and related to U.S. Pat. No. 11,774,492, filed Jun. 15, 2022, entitled “Test System Including Active Thermal Interposer Device,” Ser. No. 17/841,491. All such applications and/or patents are hereby incorporated herein by reference in their entireties. FIELD OF INVENTION Embodiments of the present invention relate to the field of integrated circuit manufacturing and testing. More specifically, embodiments of the present invention relate to systems and methods for maintaining thermal control of integrated circuits during testing thereof. BACKGROUND It is common to subject integrated circuits, either packaged or unpackaged, to environmental testing as an operation in a manufacturing process. Typically in such testing, the integrated circuit devices are subject to electrical testing, e.g., “test patterns,” to confirm functionality while being subjected to environmental stress. For example, an integrated circuit is heated and/or cooled to its specification limits while being electrically tested. In some cases, e.g., for qualification testing, an integrated circuit may be stressed beyond its specifications, for example, to determine failure points and/or to establish a “guard band” on its environmental specifications. Traditionally, such testing has included placing one or more integrated circuits and their associated test interface(s) and support hardware into an environmental chamber. The environmental chamber would heat and/or cool the integrated circuit(s) under test, known as or referred to as a device under test, or “DUT,” as well as the test interface and support hardware, to the desired test temperature. Unfortunately, use of such test chambers has numerous drawbacks. For example, the limits and/or accuracy of such testing may be degraded due to environmental limits of the test interface circuits and/or devices. The substantial air volumes, mass of mounting structures, and necessary interface devices in an environmental test chamber may impede rapid changes in the testing environment, thus limiting the testing rate. Further, placing and removing DUTs and testing apparatus into and out of such test chambers further limits rates of testing, and requires complex and expensive mechanisms to perform such insertions and removals. SUMMARY OF THE INVENTION Therefore, what is needed are systems and methods for maintaining thermal control of integrated circuits while they are being tested. What is further needed is an active thermal interposer device with thermal isolation to perform the thermal control. What is additionally needed are systems and methods for active thermal interposer devices with thermal isolation operable to control different portions of a device under test to different temperatures. Further, there is a need for systems and methods for active thermal interposer devices with thermal isolation operable to control different portions of a device under test at different heights to different temperatures. There is a still further need for systems and methods for active thermal interposer devices with thermal isolation that are compatible and complementary with existing systems and methods of testing integrated circuits. In accordance with embodiments of the present invention, an active thermal interposer (ATI) device for testing a device under test (DUT) includes a formation including one or more layers. The formation includes a first thermal zone and a second thermal zone. The first thermal zone is configured to apply thermal energy to a first thermal region of the DUT. The DUT may be an integrated circuit device. The second thermal zone is configured to apply thermal energy to a second thermal region of the DUT. The second thermal zone is configured to control a temperature of the second thermal region of the DUT independently of a temperatu