US-12618898-B1 - Neighborhood built-in self-test noise generation

Abstract

Built-in self-test (BIST) may be run on a set of circuits in proximity to a circuit under test (CUT) in an integrated circuit (IC) chip to generate noise and voltage drop conditions in the CUT. BIST may be run on the CUT while BIST is running on the set of circuits. A result of running the BIST on the CUT may be determined. The result may be associated with the noise and voltage drop conditions.

Inventors

• Adam D. Cron

Assignees

• SYNOPSYS, INC.

Dates

Publication Date

20260505

Application Date

20240426

Claims (20)

1. 1 . A method, comprising: running built-in self-test (BIST) on a set of circuits in proximity to a circuit under test (CUT) in an integrated circuit (IC) chip to generate noise and voltage drop conditions in the CUT; running BIST on the CUT while BIST is running on the set of circuits; determining a result of running the BIST on the CUT; and associating the result with the noise and voltage drop conditions.
2. 2 . The method of claim 1 , wherein the noise and voltage drop conditions are represented using an identifier which corresponds to the set of circuits.
3. 3 . The method of claim 2 , wherein the identifier includes a bit-vector.
4. 4 . The method of claim 3 , wherein a bit in the bit-vector corresponds to a circuit in the set of circuits.
5. 5 . The method of claim 2 , wherein the identifier includes shift values which are used to run BIST in the set of circuits.
6. 6 . The method of claim 1 , wherein BIST is run on the CUT by a first BIST engine.
7. 7 . The method of claim 6 , wherein BIST is run on at least one circuit in the set of circuits by a second BIST engine which is different from the first BIST engine.
8. 8 . An integrated circuit (IC), comprising: a control circuit to: run built-in self-test (BIST) on a set of circuits in proximity to a circuit under test (CUT) in the IC to generate noise and voltage drop conditions in the CUT; run BIST on the CUT while BIST is running on the set of circuits; determine a result of running the BIST on the CUT; and associate the result with the noise and voltage drop conditions.
9. 9 . The IC of claim 8 , wherein the noise and voltage drop conditions are represented using an identifier which corresponds to the set of circuits.
10. 10 . The IC of claim 9 , wherein the identifier includes a bit-vector.
11. 11 . The IC of claim 10 , wherein a bit in the bit-vector corresponds to a circuit in the set of circuits.
12. 12 . The IC of claim 9 , wherein the identifier includes shift values which are used to run BIST in the set of circuits.
13. 13 . The IC of claim 8 , wherein BIST is run on the CUT by a first BIST engine.
14. 14 . The IC of claim 13 , wherein BIST is run on at least one circuit in the set of circuits by a second BIST engine which is different from the first BIST engine.
15. 15 . A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate a digital representation of an integrated circuit (IC), the IC comprising: a control circuit to: run built-in self-test (BIST) on a set of circuits in proximity to a circuit under test (CUT) in the IC to generate noise and voltage drop conditions in the CUT, wherein the noise and voltage drop conditions are represented using an identifier which corresponds to the set of circuits; run BIST on the CUT while BIST is running on the set of circuits; determine a result of running the BIST on the CUT; and associate the result with the noise and voltage drop conditions.
16. 16 . The non-transitory computer-readable medium of claim 15 , wherein the identifier includes a bit-vector.
17. 17 . The non-transitory computer-readable medium of claim 16 , wherein a bit in the bit-vector corresponds to a circuit in the set of circuits.
18. 18 . The non-transitory computer-readable medium of claim 15 , wherein the identifier includes shift values which are used to run BIST in the set of circuits.
19. 19 . The non-transitory computer-readable medium of claim 15 , wherein BIST is run on the CUT by a first BIST engine.
20. 20 . The non-transitory computer-readable medium of claim 19 , wherein BIST is run on at least one circuit in the set of circuits by a second BIST engine which is different from the first BIST engine.

Description

TECHNICAL FIELD The present disclosure generally relates to testing and verification of an integrated circuit (IC). More specifically, the present disclosure relates to neighborhood built-in self-test (BIST) noise generation. BACKGROUND A BIST can test a circuit in an IC chip. The BIST may generally be run at any desired time, including, but not limited to, periodically, upon power-up, or in response to the occurrence of an internal or external condition. BRIEF DESCRIPTION OF THE FIGURES The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale. FIG. 1 illustrates a process for using neighborhood BIST noise generation for characterizing IC chips in accordance with some embodiments described herein. FIGS. 2A-2F illustrates neighborhood BIST noise generation in accordance with some embodiments described herein. FIG. 3 illustrates circuitry for neighborhood BIST noise generation in accordance with some embodiments described herein. FIG. 4 illustrates a process for neighborhood BIST noise generation in accordance with some embodiments described herein. FIG. 5A illustrates a process for performing a shmoo test which includes varying the amount of noise and voltage drop introduced by using neighborhood BIST noise generation in accordance with some embodiments described herein. FIG. 5B illustrates a process for detecting a degradation in a circuit in accordance with some embodiments described herein. FIG. 5C illustrates a process for detecting a defect in a circuit in accordance with some embodiments described herein. FIGS. 6A-6B illustrate a profile in accordance with some embodiments described herein. FIG. 7 illustrates a process for using a profile to recreate a field environment in accordance with some embodiments described herein. FIG. 8 illustrates an example set of processes used during the design, verification, and fabrication of an article of manufacture such as an integrated circuit to transform and verify design data and instructions that represent the integrated circuit. FIG. 9 illustrates an example machine of a computer system within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. DETAILED DESCRIPTION Aspects of the present disclosure relate to neighborhood BIST noise generation. An IC chip may include one or more BIST engines which can execute a BIST on a circuit (which may include, but is not limited to, a memory or a processor core) in the IC chip. Automatic test equipment (ATE) or a tester may communicate with a BIST engine in an IC chip via an interface. The ATE may use the BIST engine to test a circuit in the IC chip and collect diagnostic data. The diagnostic data may be communicated from the BIST engine to the ATE by using an interface for further analysis. Alternatively, the BIST engine may be instructed to perform a BIST test by a test controller circuit in the IC chip, and the diagnostic data may be collected and communicated by the test controller circuit to an off-chip entity (e.g., an analysis system) via a communication channel. A BIST engine may perform a sequence of operations on a circuit or apply a sequence of input patterns to a circuit under test (CUT) in the IC chip and check the response with an expected response to determine whether the CUT is operating as desired. A BIST engine may use a pseudo-random pattern generator to generate an entire test pattern sequence from one or more seeds which may be stored on the chip. Once an IC design has been finalized, the IC design may be provided to a semiconductor manufacturer (i.e., foundry) for volume manufacturing. During volume manufacturing, IC dies may be tested to collect pass/fail (also known as go/no-go) status of the circuits in an IC chip. Typically, when a device is manufactured and tested, the environment (voltage, signal integrity, temperature) under which that test is applied is purer than when the device is used in the field. The term “device” is used in this disclosure to generally refer to a circuit or a portion of a circuit (e.g., a logic gate). Consequently, certain defects may only occur in the field and may not be detected before the IC chip is already deployed in the field. For example, datacenter server farms have been plagued by an insidious defect, which is referred to as the Silent Data Corruption (SDC) issue in the datacenter industry. The fact that the operating conditions used during manufacturing test are different from the operating conditions in the field may be a source of these defects (which are referred to as test escapes because the manufacturing test fails to detect these defects). Embodiments