US-12618900-B2 - Wafer level electron beam prober

US12618900B2US 12618900 B2US12618900 B2US 12618900B2US-12618900-B2

Abstract

Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.

Inventors

Xianghong Tong
Wen-Hsien Chuang
Martin Von Haartman
Zhiyong Ma
Jennifer J. Huening
Hyuk Ju Ryu
Christopher Morgan
Shuai ZHAO
Ramune Nagisetty
Tuyen K. Tran

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220322

Claims (20)

1 . A system, comprising: a wafer stage to receive a wafer comprising at least one die and to position the die for testing; a probe to contact a first region of a first side of the die and to provide a test signal to the first region of the first side of the die, wherein the probe comprises a probe card comprising a plurality of probe tips to contact pads of the first side of the die, and wherein the probe tips are adjacent a perimeter of the probe card and the probe card comprises a translucent or transparent region in an interior of the probe card at least partially surrounded by the perimeter; an electron-beam (e-beam) column to provide an e-beam to a second region of the first side of the die; a detector to detect an e-beam signal from the second region of the first side of the die; and a processor circuit to generate test data based on the e-beam signal.
2 . The system of claim 1 , wherein the translucent or transparent region comprises an open region of the interior of the probe card.
3 . The system of claim 1 , further comprising: a chamber and a vacuum pump to pull a vacuum in the chamber comprising the die during test, wherein at least portions of the wafer stage, the probe, and the e-beam column are within the chamber.
4 . The system of claim 3 , wherein the wafer stage is to position a second die of the wafer for testing while a continued vacuum is maintained during testing of the die and the second die.
5 . The system of claim 4 , wherein the probe is to provide a second test signal to the second die during testing of the second die, and wherein the test signal provides a first test type and the second test signal provides a second test type other than the first test type.
6 . The system of claim 1 , wherein the first region comprises a semiconductor material or the first region comprises a metallization layer of an integrated circuit, the metallization layer comprising one of a first or second metal layer directly over a transistor contact layer.
7 . The system of claim 1 , wherein the processor circuit is to perform, based on the test signal and the e-beam signal, at least one of e-beam signal image mapping, e-beam logic state imaging, optical-electrical fault mapping, e-beam device perturbation, or stroboscopic e-beam signal image mapping.
8 . A method, comprising: receiving a wafer comprising at least one die for testing; contacting a first region of a first side of the die, wherein contacting the first region comprises contacting the first region with a probe card, the probe card comprising a plurality of probe tips adjacent a perimeter of the probe card and a translucent or transparent region in an interior of the probe card at least partially surrounded by the perimeter; providing a test signal to the first region of the first side the die; emitting an electron-beam (e-beam) on a second region of the first side of the die; and receiving an e-beam signal from the second region of the first side of the die.
9 . The method of claim 8 , further comprising: pulling a vacuum within a chamber comprising the wafer prior to said emitting the e-beam; positioning, during said pulling the vacuum, a second die of the wafer for testing; providing or receiving, during said pulling the vacuum, a second test signal to the second die; and emitting, during said pulling the vacuum and said providing the second test signal, a second e-beam on the second die.
10 . The method of claim 9 , wherein the test signal provides a first test type and the second test signal provides a second test type other than the first test type.
11 . The method of claim 8 , wherein the first region of the die comprises a metallization layer of an integrated circuit, the metallization layer comprising one of a first or second metal layer directly over a transistor contact layer of the integrated circuit.
12 . The method of claim 8 , further comprising: performing, based on test data corresponding to the e-beam signal, at least one of e-beam signal image mapping, e-beam logic state imaging, optical-electrical fault mapping, e-beam device perturbation, or stroboscopic e-beam signal image mapping.
13 . A method, comprising: pulling a vacuum in a chamber surrounding a wafer, the wafer comprising a plurality of dies for testing; positioning a first of the plurality of dies for testing of the first die; and during said pulling the vacuum in the chamber: providing a first test signal to a first region of a first side of the first die; attaining a first electron-beam (e-beam) signal from a second region of the first side of the first die during said providing the first test signal; positioning a second of the plurality of dies for testing of the second die; providing a second test signal to a first region of a first side of the second die; and attaining a second e-beam signal from a second region of the first side of the second die during said providing the second test signal.
14 . The method of claim 13 , wherein the first test signal provides a first test type and the second test signal provides a second test type other than the first test type.
15 . The method of claim 13 , wherein providing the first test signal to the first region comprises contacting the first region with a probe card.
16 . The method of claim 15 , wherein the probe card comprises a plurality of probe tips adjacent a perimeter of the probe card and a translucent or transparent region in an interior of the probe card at least partially surrounded by the perimeter.
17 . The method of claim 13 , wherein the first region of the first die comprises a metallization layer of an integrated circuit, the metallization layer comprising one of a first or second metal layer directly over a transistor contact layer of the integrated circuit.
18 . The method of claim 13 , further comprising: performing, based on test data corresponding to the first or second e-beams, at least one of e-beam signal image mapping, e-beam logic state imaging, optical-electrical fault mapping, e-beam device perturbation, or stroboscopic e-beam signal image mapping.
19 . A system, comprising: a wafer stage to receive a wafer comprising a first die and a second die, and to position the first die for testing; a probe to contact a first region of a first side of the first die and to provide a test signal to the first region of the first side of the first die; an electron-beam (e-beam) column to provide an e-beam to a second region of the first side of the first die; a detector to detect an e-beam signal from the second region of the first side of the first die; a chamber and a vacuum pump to pull a vacuum in the chamber comprising the first die during test, wherein at least portions of the wafer stage, the probe, and the e-beam column are within the chamber, and wherein the wafer stage is to position the second die of the wafer for testing while a continued vacuum is maintained during testing of the first die and the second die; and a processor circuit to generate test data based on the e-beam signal.
20 . The system of claim 19 , wherein the probe comprises a probe card comprising a plurality of probe tips to contact pads of the first side of the first die.

Description

BACKGROUND Fault isolation and failure analysis are critical parts of product design validation and debug, process development, production yield improvement, reliability testing, product certification, and product reliability qualification. The ability to identify and isolate the failing circuits and devices often defines the success or failure of a product launch. Current fault isolation at end of line is achieved by packaging units post end of line, processing and sort testing, and subsequent use of optical tools such as laser assisted device alternation, thermal induced voltage alteration, laser voltage probe/laser timing probe to locate failing devices or circuits. For example, test structures designed for offline nano- or pico-probing (i.e., extracting device electrical parameters using nano- or pico-scale probe wires) in coupon form for defect detection require breaking the structure off the wafer and loading into a nano-prober for fault isolation. Such end of line processing has a very long learning cycle for the yield and performance impact of any process skew or change due to the wait until the wafer has completed all the process, through sort tests, and build of the failing units for the optical testing to conduct debug and fault isolation. Furthermore, more advanced device structures such as double-sided metal interconnect devices cannot be analyzed using optical methods due to the blockage of the signals from both the front side and the back side of the chip. Such techniques are also susceptible to wafer depletion by pulling wafers offline for fault analysis before end of line, which reduces data turn and the ability to match to end of line data, limited ability to analyze in-line wafers, low resolution of optical techniques, lack of capability for localized quantitative circuit parameter measurement, and others. For example, the resolution of the optical approach is limited by the optical system resolution in infrared range where silicon is transparent as the signal needs to go through the silicon to reach the devices or come from the device to reach the imaging system, with current resolutions limited to about 240 nm using a 3.0 numerical aperture solid immersion lens. In addition to such limitations with resolution, other difficulties persist. It is with respect to these and other considerations that the present improvements have been needed. Thus, improvements are needed in the area of apparatuses and methodologies for performing chip debug, fault isolation, and similar operations. BRIEF DESCRIPTION OF THE DRAWINGS The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures: FIG. 1 illustrates an example electron-beam prober testing process and associated operations and device structures; FIG. 2 illustrates exemplary de-processing and sample evaluation based on test data generated using electron-beam probing; FIG. 3 illustrates exemplary automated testing based on test data generated using electron-beam probing; FIG. 4 is a flow diagram illustrating an example process for providing wafer level electron-beam probe testing; FIG. 5 is an illustration of an example wafer level electron-beam prober for performing wafer level e-beam probing; FIG. 6 is a flow diagram illustrating an example process for using electron-beam probe testing to reduce process change cycle time; FIG. 7 illustrates cross-sectional side views of example device structures for electron-beam probe testing; FIG. 8 is a flow diagram illustrating an example process for performing electron-beam prober testing; FIG. 9 is an illustrative diagram of an example system for performing electron-beam prober testing; and FIG. 10 is a functional block diagram of a computing device, all arranged in accordance with at least some implementations of the present disclosure. DETAILED DESCRIPTION One or more embodiments or implementations are now described with reference to the enclosed figures. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may also be employed in a variety of other systems and applications other than what is described herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereo