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US-12618901-B2 - Battery management module and method for detecting defective NAND gate circuit in battery management module

US12618901B2US 12618901 B2US12618901 B2US 12618901B2US-12618901-B2

Abstract

A battery management module, including a microcontroller unit, a first comparator configured to compare an input signal with a first reference signal and output a first comparison result and a NAND gate circuit configured to receive a first input from the microcontroller unit and a second input that is the first comparison result from the first comparator to generate an output signal, wherein, in an inspection mode, the first comparator is connected to a battery module tester, the microcontroller unit outputs a low-level signal as the first input, the first comparator receives the input signal from the battery module tester and outputs a low-level signal as the first comparison result and the microcontroller unit is further configured to receive the output signal of the NAND gate circuit and determine the NAND gate circuit is defective in response to the output signal of the NAND gate circuit being a low-level signal.

Inventors

  • Jin Cheol Bae

Assignees

  • SAMSUNG SDI CO., LTD.

Dates

Publication Date
20260505
Application Date
20240417
Priority Date
20231103

Claims (20)

  1. 1 . A battery management module, comprising: a microcontroller unit; a first comparator configured to compare an input signal with a first reference signal and output a first comparison result; and a NAND gate circuit configured to receive a first input from the microcontroller unit and a second input that is the first comparison result from the first comparator to generate an output signal, wherein, in an inspection mode, the first comparator is connected to a battery module tester, the microcontroller unit outputs a low-level signal as the first input, the first comparator receives the input signal from the battery module tester and outputs a low-level signal as the first comparison result, and the microcontroller unit is further configured to receive the output signal of the NAND gate circuit and determine that the NAND gate circuit is defective in response to a case where the output signal of the NAND gate circuit is a low-level signal.
  2. 2 . The battery management module as claimed in claim 1 , further comprising: a pull-up resistor having one end connected to an output terminal of the NAND gate circuit and the other end connected to a power source of the NAND gate circuit; and a second comparator configured to compare the output signal of the NAND gate circuit with a second reference signal and output a second comparison result, wherein an output terminal of the first comparator is connected to an alarm input interface included in the microcontroller unit, an output terminal of the second comparator is connected to an alarm output feedback interface included in the microcontroller unit, and the one end of the pull-up resistor is additionally connected to a NAND gate monitoring interface included in the microcontroller unit.
  3. 3 . The battery management module as claimed in claim 1 , wherein, in the inspection mode, the first comparator receives the input signal, which has a voltage lower than that of the first reference signal, from the battery module tester and outputs the low-level signal as the first comparison result.
  4. 4 . The battery management module as claimed in claim 1 , wherein the defective NAND gate circuit is indicative of an abnormal power supply state of the NAND gate circuit.
  5. 5 . The battery management module as claimed in claim 2 , wherein, in the inspection mode, the microcontroller unit receives the low-level signal output from the NAND gate circuit through the NAND gate monitoring interface, and the microcontroller unit is further configured to detect the defective NAND gate circuit based on the received low-level signal.
  6. 6 . The battery management module as claimed in claim 1 , wherein, in the inspection mode, the microcontroller unit is further configured to, in response to the determination of the defective NAND gate circuit, transmit a signal associated with the defect of the defective NAND gate circuit to the battery module tester.
  7. 7 . The battery management module as claimed in claim 6 , wherein the signal associated with the defect of the defective NAND gate circuit is transmitted to the battery module tester through a controller area network communication interface included in the microcontroller unit.
  8. 8 . The battery management module as claimed in claim 2 , wherein, in a normal operating mode, the battery management module is connected to at least one of a battery cell, a preceding battery management module, a subsequent battery management module and a battery management master module.
  9. 9 . The battery management module as claimed in claim 8 , wherein, in the normal operating mode, the microcontroller unit is further configured to receive a voltage measurement value of the at least one battery cell or a temperature measurement value of the at least one battery cell.
  10. 10 . The battery management module as claimed in claim 8 , wherein, in the normal operating mode, an alarm signal received from the preceding battery management module is used as the input signal of the first comparator.
  11. 11 . The battery management module as claimed in claim 10 , wherein, in the normal operating mode, if the alarm signal received from the preceding battery management module is a low-level signal, the low-level signal indicates that at least one preceding battery cell included in the preceding battery management module has an overvoltage state or an undervoltage state.
  12. 12 . The battery management module as claimed in claim 8 , wherein, in the normal operating mode, the output signal of the NAND gate circuit is transmitted to the subsequent battery management module.
  13. 13 . The battery management module as claimed in claim 12 , wherein, in the normal operating mode, if the output signal of the NAND gate circuit is the low-level signal, the low-level signal indicates that the at least one battery cell has an overvoltage state or an undervoltage state.
  14. 14 . The battery management module as claimed in claim 8 , wherein, in the normal operating mode, the microcontroller unit is further configured to transmit, to the battery management master module, state information of the battery management module, the state information being determined using at least one of a voltage measurement value of at least one battery cell, a temperature measurement value of at least one battery cell, the output signal of the NAND gate circuit, the first comparison result and the second comparison result.
  15. 15 . A method for detecting a defective NAND gate circuit in a battery management module, the method comprising, in an inspection mode: connecting a battery management module serving as an inspection target to a battery module tester; outputting, by a microcontroller unit, a low-level signal through a defect management interface included in the microcontroller unit; outputting, by a comparator, a low-level signal, wherein the comparator is configured to receive an input signal from the battery module tester and compare the input signal with a reference signal to output a comparison result; receiving, by a NAND gate circuit, a first input that is the low-level signal transmitted from the defect management interface included in the microcontroller unit; receiving, by the NAND gate circuit, a second input that is the low-level signal transmitted from the comparator; outputting, by the NAND gate circuit, a low-level signal based on the first input and the second input; and determining, by the microcontroller unit, that the NAND gate circuit is defective if an output signal of the NAND gate circuit is the low-level signal.
  16. 16 . The method as claimed in claim 15 , wherein the outputting, by the comparator, of the low-level signal comprises: receiving from the battery module tester the input signal having a voltage lower than that of the reference signal and outputting the low-level signal as the comparison result.
  17. 17 . The method as claimed in claim 15 , wherein the defective NAND gate circuit is indicative of an abnormal power supply state of the NAND gate circuit.
  18. 18 . The method as claimed in claim 15 , wherein the determining, by the microcontroller unit, that the NAND gate circuit is defective comprises: receiving, by the microcontroller unit, the output signal of the NAND gate circuit through a NAND gate monitoring interface; and detecting, by the microcontroller unit, the defective NAND gate circuit in response to determining that the received output signal of the NAND gate circuit is the low-level signal.
  19. 19 . The method as claimed in claim 15 , further comprising: transmitting, by the microcontroller unit, a signal associated with a defect of the defective NAND gate circuit to the battery module tester in response to determining that the NAND gate circuit is defective.
  20. 20 . The method as claimed in claim 19 , wherein the signal associated with the defect of the defective NAND gate circuit is transmitted to the battery module tester through a controller are network communication interface included in the microcontroller unit.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to and the benefit of Korean Application No. 10-2023-0151220, filed on Nov. 3, 2023, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein. BACKGROUND 1. Field Aspects of embodiments of the present disclosure relate to a battery management module and a method for detecting a defective NAND gate circuit in the battery management module. More specifically, aspects of embodiments of the present disclosure relate to the battery management module capable of detecting a defect of a NAND gate circuit and the method for detecting the defective NAND gate circuit and the method for detecting the defective NAND gate circuit. 2. Description of Related Art Secondary batteries are rechargeable batteries that are designed to be discharged and recharged multiple times. These secondary batteries are mainly used in various applications such as electronic devices (smart phones, notebook computers, tablets, etc.), electric vehicles, solar photovoltaics and emergency power supplies. In particular, lithium-ion batteries are used in various electronic devices and electric vehicles due to their high energy density and efficient charge/discharge capability. Since repeatedly charging and discharging secondary batteries, especially rechargeable batteries such as lithium-ion batteries, may shorten the lifespan thereof or degrade their performance, electric vehicles and the like are equipped with a battery management system to periodically monitor the state of the battery. Generally, the battery management system is configured to monitor a battery voltage, a current, a temperature, and the like, and manage battery charging and discharging. Meanwhile, for a function of detecting overvoltage or undervoltage of the battery cell voltage among various functions of the battery management system, a logic circuit may be employed. However, if the power supply to the logic circuit is defective, the defects may not be detected due to the input and output operation characteristics of the logic circuit. The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure, and therefore, it may contain information that does not constitute related (or prior) art. SUMMARY Embodiments include a battery management module. The battery management module includes a microcontroller unit (MCU), a first comparator configured to compare an input signal with a first reference signal and output a first comparison result and a NAND gate circuit configured to receive a first input from the microcontroller unit and a second input that is the first comparison result from the first comparator to generate an output signal, wherein, in an inspection mode, the first comparator is connected to a battery module tester, the microcontroller unit outputs a low-level signal as the first input, the first comparator receives the input signal from the battery module tester and outputs a low-level signal as the first comparison result, and the microcontroller unit is further configured to receive the output signal of the NAND gate circuit and determine that the NAND gate circuit is defective in response to the output signal of the NAND gate circuit being a low-level signal. The battery management module may further include a pull-up resistor having one end connected to an output terminal of the NAND gate circuit and the other end connected to a power source of the NAND gate circuit and a second comparator configured to compare the output signal of the NAND gate circuit with a second reference signal and output a second comparison result, wherein an output terminal of the first comparator is connected to an alarm input interface included in the microcontroller unit, an output terminal of the second comparator is connected to an alarm output feedback interface included in the microcontroller unit, and the one end of the pull-up resistor may be additionally connected to a NAND gate monitoring interface included in the microcontroller unit. In the inspection mode, the first comparator may receive the input signal, which has a voltage lower than that of the first reference signal, from the battery module tester and outputs the low-level signal as the first comparison result. The defective NAND gate circuit may be indicative of an abnormal power supply state of the NAND gate circuit. In the inspection mode, the microcontroller unit may receive the low-level signal output from the NAND gate circuit through the NAND gate monitoring interface, and the microcontroller unit may further be configured to detect the defective NAND gate circuit based on the received low-level signal. In the inspection mode, the microcontroller unit may be further configured to, in response to the determination of the defective NAND gate circuit, transmit a signal associated with the defect of the defective NA