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US-12619028-B2 - Multifunctional self-sustained hosting apparatus and related bidirectional optical sub assembly based on photonic integrated circuit

US12619028B2US 12619028 B2US12619028 B2US 12619028B2US-12619028-B2

Abstract

The invention refers to a multifunctional self-sustained hosting apparatus for photonic integrated circuit and/or related chipset system packaging comprising a processed wafer ( 1 ); and at least a cavity ( 2 ), wherein said cavity ( 2 ) is configured to receive a chipset or an optical lens; and at least a V-groove ( 3 ), which is configured for receiving at least an in/out optical fiber and optically align said optical fiber with an optical endface of a chipset. The invention also refers to a bidirectional optical sub assembly based on photonic integrated circuit, which comprises said hosting apparatus. The hosting apparatus enables PIC&IC co-packaging allowing to answer current and future requirements in diverse PIC applications. The apparatus provides electrical interconnections using direct-current lines and radio frequency lines, and may host a plurality of chipsets with different dimensions and orientations, providing a high-precision optical coupling between arrays of optical fibers and optical endface of chipsets.

Inventors

  • Francisco Manuel RUIVO RODRIGUES
  • Nuno Ricardo PEREIRA BASTOS
  • Hugo Daniel BARBOSA NETO
  • Yahya SHEIKHNEJAD
  • Pedro Nuno LOPES SILVA
  • António Luís JESUS TEIXEIRA

Assignees

  • PICADVANCED S.A.

Dates

Publication Date
20260505
Application Date
20220525
Priority Date
20210531

Claims (20)

  1. 1 . A multifunctional self-sustained hosting apparatus for photonic integrated circuit and/or related chipset system packaging comprising: a processed wafer ( 1 ); and a plurality of cavities ( 2 ) embedded on a top surface of the processed wafer ( 1 ); and at least a V-groove ( 3 ), which is formed on the top surface of the processed wafer ( 1 ) or in a submount ( 10 ); and wherein the submount ( 10 ) is attached to a recess in the processed wafer ( 1 ), and said recess and said submount ( 10 ) are arranged at an adjacent position in relation to at least one cavity ( 2 ); and wherein said V-groove extends from an edge of said processed wafer ( 1 ) or said submount ( 10 ) toward at least one cavity ( 2 ); and wherein said V-groove ( 3 ) is configured for receiving at least an in/out optical fiber ( 7 ) and optically align said in/out optical fiber ( 7 ) with an optical endface of a chipset ( 8 ); wherein the multifunctional self-sustained hosting apparatus further comprises a radio frequency line ( 13 ) embedded on the processed wafer ( 1 ) and, optionally, further comprises a direct-current line ( 4 ) embedded on the processed wafer ( 1 ), characterized in that each cavity ( 2 ) is configured to receive at least one from the group consisting of a chipset ( 9 ) and an optical lens ( 15 ), and the cavities ( 2 ) are disposed in an arbitrary orientation across the processed wafer ( 1 ).
  2. 2 . The multifunctional self-sustained hosting apparatus, according to claim 1 , characterized by the cavities ( 2 ) are disposed longitudinally across the processed wafer ( 1 ), forming at least a row of cavities ( 2 ).
  3. 3 . The multifunctional self-sustained hosting apparatus, according to claim 1 , characterized in that a plurality of cavities ( 2 ), that are disposed transversely across the processed wafer ( 1 ), form at least a column of cavities ( 2 ).
  4. 4 . The multifunctional self-sustained hosting apparatus, according to claim 1 , characterized by the cavities ( 2 ) are disposed in a row at an acute angle in relation to the extension of the V-groove ( 3 ).
  5. 5 . The multifunctional self-sustained hosting apparatus, according to claim 1 , characterized by comprising a temperature sensor ( 5 ), which is configured for sensing temperature to be used for thermal management.
  6. 6 . The multifunctional self-sustained hosting apparatus, according to claim 5 , characterized by the temperature sensor ( 5 ) is a thermistor.
  7. 7 . The multifunctional self-sustained hosting apparatus, according to claim 6 , characterized by the temperature sensor ( 5 ) is a built-in integrated planar thin film thermistor.
  8. 8 . The multifunctional self-sustained hosting apparatus, according to claim 1 , characterized by at least a V-groove ( 3 ) is disposed at an acute angle in relation to the longitudinal extension of the optical endface of a chipset ( 8 ).
  9. 9 . The multifunctional self-sustained hosting apparatus, according to claim 1 , characterized by comprising a resistor ( 14 ) embedded on the processed wafer ( 1 ).
  10. 10 . The multifunctional self-sustained hosting apparatus, according to claim 9 , characterized by the resistor ( 14 ) embedded on the processed wafer ( 1 ) is a built-in integrated thin film resistor.
  11. 11 . A bidirectional optical sub assembly based on photonic integrated circuit comprising a multifunctional self-sustained hosting apparatus for photonic integrated circuit and/or related chipset system packaging, wherein said hosting apparatus is configured to unify and integrate at least one photonic integrated circuit and one chipset ( 9 ) within a miniaturized single entity, and comprises: a processed wafer ( 1 ); and a plurality of cavities ( 2 ) embedded on a top surface of the processed wafer ( 1 ); and at least a V-groove ( 3 ), which is formed on the top surface of the processed wafer ( 1 ) or in a submount ( 10 ); and wherein the submount ( 10 ) is attached to a recess in the processed wafer ( 1 ), and said recess and said submount ( 10 ) are arranged at an adjacent position in relation to at least one cavity ( 2 ); and wherein said V-groove extends from an edge of said processed wafer ( 1 ) or said submount ( 10 ) toward at least one cavity ( 2 ); and wherein said V-groove ( 3 ) is configured for receiving at least an in/out optical fiber ( 7 ) and optically align said in/out optical fiber ( 7 ) with an optical endface of a chipset ( 8 ); and characterized in that each cavity ( 2 ) is configured to receive at least one from the group consisting of a chipset ( 9 ) and an optical lens ( 15 ), and the cavities ( 2 ) are disposed in an arbitrary orientation across the processed wafer ( 1 ); and the bidirectional optical sub assembly based on photonic integrated circuit further comprises at least an in/out optical fiber ( 7 ) connected to the V-groove ( 3 ) of said hosting apparatus; and the bidirectional optical sub assembly based on photonic integrated circuit further comprises the optical endface of a chipset ( 8 ) optically connected to an end part of the in/out optical fiber ( 7 ) or the optical lens ( 15 ) by means of an edge coupling; wherein the hosting apparatus comprises a radio frequency line ( 13 ) embedded on the processed wafer ( 1 ) and, optionally, further comprises a direct-current line ( 4 ) embedded on the processed wafer ( 1 ); and wherein at least a chipset ( 9 ) is connected by at least an electrical connection to the radio frequency line ( 13 ).
  12. 12 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 11 , characterized by the cavities ( 2 ) are disposed longitudinally across the processed wafer ( 1 ) in the hosting apparatus, forming at least a row of cavities ( 2 ).
  13. 13 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 12 , characterized in that a plurality of cavities ( 2 ), that are disposed transversely across the processed wafer ( 1 ) in the hosting apparatus, form at least a column of cavities ( 2 ).
  14. 14 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 12 , characterized by the cavities ( 2 ) are disposed in a row at an acute angle in relation to the extension of the V-groove ( 3 ).
  15. 15 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 11 , characterized by the hosting apparatus comprises a temperature sensor ( 5 ), which is configured for sensing temperature of the bidirectional optical sub assembly based on photonic integrated circuit to be used for thermal management.
  16. 16 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 15 , characterized by the temperature sensor ( 5 ) is a thermistor, wherein the thermistor is a built-in integrated planar thin film thermistor, wherein said thermistor is configured to execute thermal management and temperature controlling for a temperature-sensitive chipset ( 9 ).
  17. 17 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 11 , characterized by comprising a resistor ( 14 ) embedded on the processed wafer ( 1 ), wherein said resistor ( 14 ) is configured for insertion of a heat flow in the bidirectional optical sub assembly based on photonic integrated circuit.
  18. 18 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 17 , characterized by the resistor ( 14 ) is a built-in integrated thin film resistor.
  19. 19 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 11 , characterized by at least a V-groove ( 3 ) is disposed at an acute angle in relation to the longitudinal extension of the optical endface of a chipset ( 8 ).
  20. 20 . The bidirectional optical sub assembly based on photonic integrated circuit, according to claim 11 , characterized by the connection between the in/out optical fiber ( 7 ) and the V-groove ( 3 ) is performed by means of an adhesive.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a National Phase of PCT Patent Application No. PCT/IB2022/054917 having International filing date of May 25, 2022, which claims the benefit of priority of Portugal Patent Application No. 117262, filed May 31, 2021, the contents of which are all incorporated herein by reference in their entirety. TECHNICAL FIELD The present invention refers to a multifunctional self-sustained hosting apparatus configured for photonic integrated circuit and/or related chipset system packaging as well as applications that involve emitting and/or collecting light for pre-processing or post-processing and a related bidirectional optical sub assembly (BOSA) based on photonic integrated circuit (PIC). The applications of said hosting apparatus comprise photonic integrated circuits (PICs) and integrated circuits (IC) co-packaging, hosting of arbitrary oriented multiple chipsets and optically aligning of arbitrary-oriented multiple optical fibers, either through direct coupling or through lenses alignment taking advantage of the cavities in the apparatus. The present invention also refers to a BOSA based on PIC comprising said hosting apparatus, wherein the hosting apparatus is configured to provide a high-precision PIC&IC co-packaging, including but not limited to the optical alignment of an optical fiber array with optoelectronic devices by means of V-groove microstructures, while covering thermo-electrical management and electrical interconnections. Therefore, the present invention refers to a host platform for integrated circuit packaging providing functionalities of bidirectional optical alignment, electrical interconnection and thermal management. BACKGROUND ART Recently, industrial trends strongly favor the concepts of high density, low-power consumption and low-cost applications of Datacom and Telecom pluggable transceiver modules. Hence, there are various challenges in the design of high-performance compact optical transceivers. In a continuous competition for higher data bitrate, the next generation of passive optical network has been imposing higher standards on the optical transceivers. Moreover, the growing trend of multichannel optical devices (e.g., wavelength division multiplexing network) demands for accurate low-loss high-resilient electro-optical packaging. This fact implied the profitability of the proposed solution to the wide telecommunication market. Therefore, a higher level of integration and miniaturization (HLI&M) in PIC and associated packaging are essential in order to develop devices that meet the current standards and demands. This problem is already considered as the most significant bottleneck in the development of commercially relevant integrated photonic devices. Overcoming this problem will be a golden key to considerably reduce the necessary amount of materials to produce said integrated photonic devices and the related production costs. In this context, a higher level of integration with the capability of handling an array of optical fibers demands less usage of active components, gather all required functionalities and simultaneously merge and unify these functionalities into a single small device. The optical fibers are an essential part of photonic devices and have to be strictly managed, because a few microns deviation could lead to a significant optical power loss. In order to comply with HLI&M and at the same time achieve this goal, optical fibers must be passively aligned with optoelectronic devices. This part of the problem is addressed by some prior art documents. For example, the most common geometry for passive alignment of an optical fiber is a V-groove on a substrate as disclosed in the U.S. Patent No. U.S. Pat. No. 7,031,576B2 of National Semiconductor Corp., entitled “CONNECTORIZED SILICON BENCH FOR PASSIVELY ALIGNING OPTICAL FIBERS” and published on Apr. 18, 2006, and U.S. Patent No. US6888989B1 of “Phosistor Technologies Inc., entitled “FIBER ARRAY WITH V-GROOVE CHIP AND MOUNT” and published on May 3, 2005. The former which is incorporated by reference herein, discusses the connectorized silicon bench with a groove formed in the bench to accommodate an optical fiber and together with a ferrule including a recess region will assist passive alignment. The latter, however, the molded mount of non-crystalline polymer material was configured to have a channel for aligning one silicon chip having a few number of V-grooves. The optical fibers were securely sandwiched by two such molded mounts with silicon chips opposing one another to align optical fibers in between. The U.S. patent application No. US20190285813A1 of Cisco Tech Inc., entitled “FIBER TO CHIP ALIGNMENT USING PASSIVE VGROOVE STRUCTURES” and published on Sep. 19, 2019, which is hereby incorporated herein by reference in its entirety, endeavors to address the above challenge by providing a substrate comprising a plurality of waveguides arranged at a predefined dept