US-12619037-B2 - Integrated circuit device facilitating same-side optical and electrical testing

US12619037B2US 12619037 B2US12619037 B2US 12619037B2US-12619037-B2

Abstract

Some embodiments relate to an integrated circuit (IC) device that includes a first substrate including an optical lens at a frontside surface of the first substrate, an electrical IC structure disposed proximate a backside surface of the first substrate, and a photonic IC structure disposed proximate a backside surface of the electrical IC structure. The photonic IC structure includes a second substrate providing a backside surface of the photonic IC structure; a photodetector, a grating coupler, and an inverse grating coupler disposed over a frontside surface of the second substrate; and a reflector disposed at a frontside surface of the photonic IC structure. The grating coupler and the inverse grating coupler are configured to direct light from the optical lens and the backside surface of the second substrate, respectively, to the photodetector. The reflector is configured to direct light from the inverse grating coupler back to the inverse grating coupler.

Inventors

Xin-Hua Huang
Kuo-Hao Lee
Jung-Kuo Tu
Kejun Xia
Tse-En Chang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20231017

Claims (20)

1 . An integrated circuit (IC) device, comprising: a first substrate comprising an optical lens at a top surface of the first substrate; an electrical IC structure disposed under the first substrate; and a photonic IC structure disposed under the electrical IC structure, the photonic IC structure comprising: a second substrate providing a bottom surface of the photonic IC structure; a photodetector, a grating coupler, and an inverse grating coupler disposed on the second substrate; and a reflector disposed at a top surface of the photonic IC structure proximate the electrical IC structure; wherein: the grating coupler is configured to receive first light via the optical lens, the first substrate, and the electrical IC structure and to direct the first light to the photodetector; the inverse grating coupler is configured to receive second light via a backside surface of the second substrate and to direct the second light to the photodetector; and the reflector is configured to receive third light from the inverse grating coupler and to direct the third light back to the inverse grating coupler, wherein the inverse grating coupler is further configured to direct the third light to the photodetector.
2 . The IC device of claim 1 , wherein: the photonic IC structure further comprises a conductive structure having a plurality of metal layers interconnected with a plurality of vias, the conductive structure configured to electrically couple the photodetector to the electrical IC structure; and an uppermost metal layer of the plurality of metal layers lies in a same plane as the reflector.
3 . The IC device of claim 2 , wherein the reflector is electrically isolated from the conductive structure.
4 . The IC device of claim 1 , wherein the reflector comprises at least one of titanium or an aluminum-copper alloy.
5 . The IC device of claim 1 , wherein a thickness of the reflector ranges from 1000 angstroms to 14000 angstroms.
6 . The IC device of claim 1 , wherein at least one of a width and a length of the reflector ranges from 20 microns to 100 microns.
7 . The IC device of claim 1 , wherein the reflector is aligned with the inverse grating coupler in a plan view of the IC device.
8 . The IC device of claim 1 , wherein the reflector is a single contiguous reflective element in a plan view of the IC device.
9 . The IC device of claim 1 , wherein the reflector comprises a two-dimensional array of spaced reflective elements.
10 . An integrated circuit (IC) device, comprising: an electrical IC structure comprising a conductive layer; an optical lens disposed proximate a frontside surface of the electrical IC structure; a photonic IC structure disposed proximate a backside surface of the electrical IC structure, the photonic IC structure comprising: a photodetector; a grating coupler optically coupled to the photodetector and configured to direct first light received from the optical lens; an inverse grating coupler optically coupled to the photodetector and configured to direct second light received from a backside surface of the photonic IC structure to the photodetector; a reflector configured to reflect third light from the inverse grating coupler back to the inverse grating coupler, wherein the inverse grating coupler directs the third light to the photodetector; and a first conductive structure coupling the photodetector to the conductive layer; and a contact disposed proximate the backside surface of the photonic IC structure and coupled to a second conductive structure of the photonic IC structure coupling the contact to the conductive layer.
11 . The IC device of claim 10 , wherein: the electrical IC structure comprises an electrical IC die; and a plurality of electrical IC dice comprises the electrical IC die; and each of the plurality of electrical IC dice are bonded to the photonic IC structure.
12 . The IC device of claim 10 , further comprising: a first waveguide configured to optically couple the grating coupler to the photodetector; and a second waveguide configured to optically couple the inverse grating coupler to the photodetector.
13 . The IC device of claim 10 , wherein: none of the grating coupler, the inverse grating coupler, and the electrical IC structure overlap each other in a plan view of the IC device; and each of the grating coupler, the inverse grating coupler, and the electrical IC structure overlaps the photonic IC structure in the plan view of the IC device.
14 . A method, comprising: providing a substrate for a photonic IC structure; forming a grating coupler, an inverse grating coupler, and a photodetector over the substrate, the grating coupler and the inverse grating coupler optically coupled to the photodetector; forming a first conductive structure coupling the photodetector to a frontside surface of the photonic IC structure; forming a second conductive structure coupled to the frontside surface of the photonic IC structure; forming a reflector at the frontside surface of the photonic IC structure, the reflector configured to reflect first light received from the inverse grating coupler back to the inverse grating coupler; creating an electrical IC die comprising a conductive layer; bonding a backside surface of the electrical IC die to the frontside surface of the photonic IC structure to couple the conductive layer to the first conductive structure and the second conductive structure; and bonding an optical lens to a frontside surface of an electrical IC structure that includes the electrical IC die, the optical lens configured to direct second light via the electrical IC structure to the grating coupler.
15 . The method of claim 14 , wherein: forming a via in the substrate of the photonic IC structure by way of a backside surface of the photonic IC structure; and forming a contact over the backside surface of the photonic IC structure to couple the contact to the second conductive structure.
16 . The method of claim 14 , wherein: the reflector lies in a same plane as a layer of each of the first conductive structure and the second conductive structure; and the reflector is electrically isolated from both the first conductive structure and the second conductive structure.
17 . The method of claim 14 , wherein: the substrate comprises a first semiconductor layer; and the method further comprises: forming a first dielectric layer over the first semiconductor layer; and forming a second semiconductor layer over the first dielectric layer.
18 . The method of claim 17 , wherein forming the grating coupler and the inverse grating coupler comprises: etching a plurality of individual trenches of the grating coupler in the second semiconductor layer that do not reach the first dielectric layer; etching a single region for the inverse grating coupler in the second semiconductor layer to the first dielectric layer; depositing a dielectric material to fill the plurality of individual trenches and the single region and to form a second dielectric layer; forming an etch stop layer over the second dielectric layer; etching the single region to leave a sidewall and a plurality of individual ridges of the dielectric material; depositing polycrystalline silicon to fill the etched single region; and removing the etch stop layer.
19 . The method of claim 18 , wherein the plurality of individual ridges extend from the first dielectric layer partially into the single region.
20 . The method of claim 18 , wherein the reflector substantially covers the single region in a plan view of the photonic IC structure.

Description

BACKGROUND One result of continued advancement in integrated circuit (IC) technology is the increased integration of electrical and optical functionality in a single IC device. To support such integration, testing of both electrical functions (e.g., using circuit probe (CP) testing) and optical functions of the device (e.g., using a laser for optical testing input) is performed prior to customer delivery to reduce or eliminate the provision of non-functional or poor-performing IC devices. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A illustrates a schematic process view of some embodiments of fabrication of an IC device that facilitates same-side electrical and optical testing, according to the present disclosure. FIGS. 1B and 1C illustrate a schematic side view and a schematic plan view, respectively, of some embodiments of an IC device that facilitates same-side electrical and optical testing, according to the present disclosure. FIG. 2 illustrates a structural side view of some embodiments of an IC device that facilitates same-side electrical and optical testing, according to the present disclosure. FIGS. 3A through 3G illustrate side views of some embodiments of an IC device that facilitates same-side electrical and optical testing at various stages of manufacture, according to the present disclosure. FIG. 4 illustrates a methodology of forming an IC device that facilitates same-side electrical and optical testing, in accordance with some embodiments. FIGS. 5A through 5F illustrate cross-sectional views of some embodiments of a semiconductor structure including a grating coupler and an inverse grating coupler for an IC device that facilitates same-side electrical and optical testing, according to the present disclosure. FIG. 6 illustrates a methodology of forming the semiconductor structure of FIGS. 5A through 5F, in accordance with some embodiments. FIGS. 7A through 7C illustrate a plan view of some embodiments of an inverse grating coupler and associated reflector for an IC device that facilitates same-side electrical and optical testing, according to the present disclosure. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As further integration of optical and associated electrical functions in a single IC device continues, the simultaneous testing of both types of functionality in the device is considered important from both a photonics wafer acceptance test (WAT) point of view and a chip probe (CP) testing perspective. However, this simultaneous testing may be challenging, as accessible electrical input/output (I/O) points may be positioned on an opposite side of the device from the optical I/O locations, and some testing equipment and processes may not be compatible with accessing both sides of the IC device simultaneously. Providing testing optical I/O paths that are on the opposing side of the device from the optical I/O paths used during normal operation may be possible. However, these testing paths may suffer from significant optical signal loss due to undesirable diffraction and scattering effects, thus rendering th