US-12619038-B2 - Approach to prevent plating at v-groove zone in photonics silicon during bumping or pillaring

US12619038B2US 12619038 B2US12619038 B2US 12619038B2US-12619038-B2

Abstract

Embodiments disclosed herein include electronic devices and methods of forming electronic devices. In an embodiment, an electronic device comprises a die. In an embodiment, the die comprises a semiconductor substrate, a bump field over the semiconductor substrate, and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate. In an embodiment, the V-groove is free from conductive material. In an embodiment, the electronic device further comprises an optical fiber inserted into the V-groove.

Inventors

Santosh SHAW

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220331

Claims (8)

1 . An electronic device, comprising: a die, wherein the die comprises: a semiconductor substrate; a bump field over the semiconductor substrate; and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate, and wherein the V-groove is free from conductive material; an optical fiber inserted into the V-groove; and a spot size converter at an end of the V-groove away from the edge of the semiconductor substrate, the spot size converter intervening between the end of the V-groove and the bump field.
2 . The electronic device of claim 1 , wherein the optical fiber is optically coupled to the spot size converter.
3 . The electronic device of claim 1 , further comprising a plurality of V-grooves, and a plurality of optical fibers, wherein individual ones of the plurality of optical fibers are inserted into individual ones of the plurality of V-grooves.
4 . The electronic device of claim 1 , wherein the semiconductor substrate comprises silicon.
5 . The electronic device of claim 1 , wherein the die is coupled to a package substrate.
6 . The electronic device of claim 5 , wherein the package substrate is coupled to a board.
7 . An electronic system, comprising: a board; a package substrate coupled to the board; a die coupled to the package substrate, wherein the die comprises: a semiconductor substrate; a bump field over the semiconductor substrate; and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate, and wherein the V-groove is free from conductive material; an optical fiber inserted into the V-groove; and a spot size converter at an end of the V-groove away from the edge of the semiconductor substrate, the spot size converter intervening between the end of the V-groove and the bump field.
8 . The electronic system of claim 7 , wherein the spot size converter is optically coupled to the optical fiber.

Description

GOVERNMENT LICENSE RIGHTS This invention was made with Government support under Agreement No. HR0011-19-3-0003, awarded by DARPA. The Government has certain rights in the invention. TECHNICAL FIELD Embodiments of the present disclosure relate to optical packages, and more particularly to optical packages with V-grooves that are free from bumping material. BACKGROUND In optoelectronic dies, V-grooves are etched into the surface of the semiconductor substrate. The V-grooves are used in order to provide passive fiber alignment during the fiber attach process. After the V-grooves are formed, a bumping process is implemented on the semiconductor substrate. The bumping process may include the use of a spin coated photoresist material. Unfortunately, the spin coating process may negatively interact with the V-grooves. For example, the topology of the V-grooves may result in the formation of bubbles in the photoresist material over the V-grooves. The bubbles may provide openings through the photoresist material. Ultimately, material is plated onto the V-groove region during the bumping process. Any residue at the V-groove area will deteriorate the fiber attach coupling efficiency and result in dB losses. Laminated photoresist materials have been proposed instead of the spin coating process in order to provide a solution for photoresist bubble formation. In such architectures, photoresist is laminated as a semi-solid material in order to prevent bubble formation. However, lamination based photoresist processes are not standard processes for bumping patterning. As such new equipment would be needed. Additionally, the throughput of laminated photoresist processes is far less compared to spin-coating based photoresist processes. Uniform adhesion of the resist across the wafer, especially at the edges, is also challenging to accomplish. Due to the nature of the process, laminated photoresist is not currently an option for fine features and multiple steps of bumping. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a plan view illustration of a die with V-grooves, in accordance with an embodiment. FIG. 1B is a cross-sectional illustration of the die in FIG. 1A, in accordance with an embodiment. FIG. 1C is a plan view illustration of the die after an under bump metallization (UBM) layer is disposed over the surface of the die, in accordance with an embodiment. FIG. 1D is a cross-sectional illustration of the die in FIG. 1C, in accordance with an embodiment. FIG. 1E is a plan view illustration of the die after a photoresist is disposed over the die and a bubble is formed over a V-groove, in accordance with an embodiment. FIG. 1F is a cross-sectional illustration of the die in FIG. 1E, in accordance with an embodiment. FIG. 1G is a plan view illustration of the die after a bumping process is implemented that plates metal in the bubble, in accordance with an embodiment. FIG. 1H is a cross-sectional illustration of the die in FIG. 1G, in accordance with an embodiment. FIG. 1I is a plan view illustration of the die after the photoresist is removed, in accordance with an embodiment. FIG. 1J is a cross-sectional illustration of the die in FIG. 1I, in accordance with an embodiment. FIG. 2A is a plan view illustration of a die with a plurality of V-grooves, in accordance with an embodiment. FIG. 2B is a cross-sectional illustration of the die in FIG. 2A, in accordance with an embodiment. FIG. 2C is a plan view illustration of the die after a UBM layer is disposed over the surface of the die, in accordance with an embodiment. FIG. 2D is a cross-sectional illustration of the die in FIG. 2C, in accordance with an embodiment. FIG. 2E is a plan view illustration of the die after a first photoresist layer is disposed over the die, in accordance with an embodiment. FIG. 2F is a cross-sectional illustration of the die in FIG. 2E, in accordance with an embodiment. FIG. 2G is a plan view illustration of the die after an opening is formed into the photoresist layer to expose the V-groove region of the die, in accordance with an embodiment. FIG. 2H is a cross-sectional illustration of the die in FIG. 2G, in accordance with an embodiment. FIG. 2I is a plan view illustration of the die after the UBM is removed from the V-groove region of the die, in accordance with an embodiment. FIG. 2J is a cross-sectional illustration of the die in FIG. 2I, in accordance with an embodiment. FIG. 2K is a plan view illustration of the die after the first photoresist layer is removed, in accordance with an embodiment. FIG. 2L is a cross-sectional illustration of the die in FIG. 2K, in accordance with an embodiment. FIG. 2M is a plan view illustration of the die after a second photoresist is disposed over the surface of the die and a bubble is formed in the V-groove region, in accordance with an embodiment. FIG. 2N is a cross-sectional illustration of the die in FIG. 2M, in accordance with an embodiment. FIG. 2O is a plan view illustration of the die after openings