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US-12619159-B2 - Method for modeling measurement data over a substrate area and associated apparatuses

US12619159B2US 12619159 B2US12619159 B2US 12619159B2US-12619159-B2

Abstract

Disclosed is a method for determining a process correction for at least a first process of a lithographic process, comprising at least the first process performed on at least a first substrate using at least a first apparatus and a second process performed on at least said first substrate using at least a second apparatus, where a correction actuation capability of the first apparatus differs from the second apparatus, comprising: obtaining metrology data relating to said first substrate; modeling said metrology data using a first model, the model being related to said first apparatus; and controlling said first process based on the modeled metrology data; the modeling step and/or an additional processing step comprises distributing a penalty in a performance parameter across said first process and said second process such that the distributed penalties in the performance parameter are within their respective specifications of the performance parameter.

Inventors

  • Gijs TEN HAAF
  • Everhardus Cornelis Mos
  • Hans Erik Kattouw
  • Ralph Brinkhof

Assignees

  • ASML NETHERLANDS B.V.

Dates

Publication Date
20260505
Application Date
20240209
Priority Date
20210812

Claims (20)

  1. 1 . A method for determining a process correction for at least a first process of a lithographic process, said lithographic process comprising at least the first process performed on at least a first substrate using at least a first apparatus and a second process performed on at least said first substrate using at least a second apparatus, where a correction actuation capability of the first apparatus differs from the second apparatus, the method comprising: obtaining metrology data relating to said first substrate; modeling said metrology data using a first model, said first model being related to said first apparatus; and controlling said first process based on the modeled metrology data; wherein said modeling and/or an additional processing comprises distributing a lithographic error penalty in a lithographic performance parameter across said first process and said second process such that distributed lithographic error penalties in the lithographic performance parameter for said first and second processes are within respective specifications of said first and second processes for the performance parameter.
  2. 2 . The method of claim 1 , wherein said modeling and/or said additional processing further comprises fitting the first model to the metrology data so as to generate a first set of model parameters.
  3. 3 . The method of claim 1 , wherein said distributing the lithographic error penalty comprises optimizing a cost function comprising a sum of a lithographic error penalty in the lithographic performance parameter for the first process and a lithographic error penalty in the lithographic performance parameter for the second process.
  4. 4 . The method of claim 3 , wherein said cost function comprises a sum of each of said lithographic error penalties per direction of a substrate plane.
  5. 5 . The method of claim 3 , wherein said sum is a weighted sum, and the method comprises determining the weights for said weighted sum based on required specifications for the lithographic performance parameter.
  6. 6 . The method of claim 3 , wherein said modeling and/or an additional processing comprises modifying said first set of model parameters to obtain a modified set of model parameters; and determining the lithographic error penalty in said lithographic performance parameter for said first process based on a deviation from said first set of model parameters when applying said modified set of model parameters to said first model.
  7. 7 . The method of claim 6 , wherein said modeling and/or said additional processing further comprises mapping the first set of model parameters to said modified set of model parameters using a model mapping matrix.
  8. 8 . The method of claim 3 , comprising determining the lithographic error penalty in said lithographic performance parameter for said second process based on the difference of said modified set of model parameters and a converted set of model parameters that is calculated with a conversion matrix that converts said modified set of model parameters into a second set of model parameters to the model basis functions of said first model, said second set of model parameters being related to a second model which is related to the second apparatus.
  9. 9 . The method of claim 2 , wherein said fitting comprises imposing a regularization based on an estimated lithographic error penalty in said lithographic performance parameter for said second process.
  10. 10 . The method of claim 9 , wherein said regularization is equal to said estimated lithographic error penalty in said lithographic performance parameter for said second process.
  11. 11 . The method of claim 9 , wherein said fitting comprises minimizing a cost function comprising first model residuals of said metrology data and said estimated lithographic error penalty in said lithographic performance parameter for said second process.
  12. 12 . The method of claim 1 , wherein said metrology data comprises alignment data for the first process and said first model comprises an alignment model.
  13. 13 . The method of claim 1 , wherein the second apparatus is a lithographic exposure apparatus and the second process is a lithographic exposure process.
  14. 14 . The method of claim 1 , wherein the second apparatus is a bonding apparatus and the second process is a bonding process for bonding said first substrate to a second substrate, subsequent to lithographic performance of said lithographic exposure process.
  15. 15 . The method of claim 14 , wherein said metrology data relates to both of said first substrate and second substrate, and said distributing the lithographic error penalty in the lithographic performance parameter across said first process and second process comprises distributing said lithographic error penalties in the lithographic performance parameter for said first process over said first substrate and second substrate.
  16. 16 . The method of claim 1 , wherein the first apparatus is a lithographic exposure apparatus and first process is a lithographic exposure process.
  17. 17 . The method of claim 16 , wherein the first process comprises exposing lithographically a layer on the first substrate.
  18. 18 . The method of claim 17 , wherein said metrology data relates to at least a final layer, said final layer being the final layer exposed on said first substrate prior to said second process.
  19. 19 . The method of claim 18 , wherein said metrology data relates to one or more additional layers other than said final layer exposed on said first substrate, and said distributing the lithographic error penalty in the lithographic performance parameter across said first process and said second process comprises distributing said lithographic error penalties in the lithographic performance parameter for said first process over said one or more additional layers in addition to said final layer.
  20. 20 . The method of claim 1 , wherein controlling said first process comprises applying the process correction within the first apparatus so as to distribute the lithographic error penalty in the lithographic performance parameter across said first process and said second process.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority of International application PCT/EP2022/070828, filed on 25 Jul. 2022, which claims priority of EP application 21191014.6, filed on 12 Aug. 2021. These applications are incorporated herein by reference in their entireties. FIELD The present disclosure relates to processing of substrates for the production of, for example, semiconductor devices. BACKGROUND A lithographic apparatus is a machine constructed to apply a desired pattern onto a substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A lithographic apparatus may, for example, project a pattern (also often referred to as “design layout” or “design”) at a patterning device (e.g., a mask) onto a layer of radiation-sensitive material (resist) provided on a substrate (e.g., a wafer). To project a pattern on a substrate a lithographic apparatus may use radiation. The wavelength of this radiation determines the minimum size of features which can be formed on the substrate. Typical wavelengths currently in use are about 365 nm (i-line), about 248 nm, about 193 nm and about 13 nm. A lithographic apparatus, which uses extreme ultraviolet (EUV) radiation, having a wavelength within the range 4-20 nm, for example 6.7 nm or 13.5 nm, may be used to form smaller features on a substrate than a lithographic apparatus which uses, for example, radiation with a wavelength of about 193 nm. Low-k1 lithography may be used to process features with dimensions smaller than the classical resolution limit of a lithographic apparatus. In such a process, the resolution formula may be expressed as CD=k1×λ/NA, where λ is the wavelength of radiation employed, NA is the numerical aperture of the projection optics in the lithographic apparatus, CD is the “critical dimension” (generally the smallest feature size printed, but in this case half-pitch) and k1 is an empirical resolution factor. In general, the smaller k1 the more difficult it becomes to reproduce the pattern on the substrate that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps may be applied to the lithographic projection apparatus and/or design layout. These include, for example, but not limited to, optimization of a numerical aperture (NA,) a customized illumination scheme, use of one or more phase shifting patterning devices, optimization of the design layout such as optical proximity correction (OPC) in the design layout, or other methods generally defined as resolution enhancement techniques (RET). Additionally or alternatively, one or more tight control loops for controlling a stability of the lithographic apparatus may be used to improve reproduction of the pattern at low k1. Effectiveness of the control of a lithographic apparatus may depend on characteristics of individual substrates. For example, a first substrate processed by a first processing tool prior to processing by the lithographic apparatus (or any other process step of the manufacturing process, herein referred to generically as a manufacturing process step) may benefit from (slightly) different control parameters than a second substrate processed by a second processing tool prior to processing by the lithographic apparatus. The accurate placement of patterns on the substrate is a chief challenge for reducing the size of circuit components and other products that may be produced by lithography. In particular, the challenge of measuring accurately the features on a substrate which have already been laid down is a critical step in being able to align successive layers of features in superposition accurately enough to produce working devices with a high yield. So-called overlay should, in general, be achieved within a few tens of nanometers in today's sub-micron semiconductor devices, down to a few nanometers in the most critical layers. Consequently, modern lithography apparatuses involve extensive measurement or ‘mapping’ operations prior to the step of actually exposing or otherwise patterning the substrate at a target location. So-called advanced alignment models have been and continue to be developed to model and correct more accurately non-linear distortions of the wafer ‘grid’ that are caused by processing steps and/or by the lithographic apparatus itself. Not all distortions are correctable during exposure, however, and it remains important to trace and eliminate as many causes of such distortions as possible. These distortions of the wafer grid are represented by measurement data associated with mark position. The measurement data are obtained from measurements of wafers. An example of such measurements are alignment measurements of alignment marks performed using an alignment system in a lithographic apparatus prior to exposure. It would be desirable to improve modeli