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US-12619163-B1 - Manufacturing of test structures using e-beam lithography for use in characterization and quality control of metrology tools used in semiconductor manufacturing

US12619163B1US 12619163 B1US12619163 B1US 12619163B1US-12619163-B1

Abstract

A method is provided for making test structures suitable for characterizing and calibrating semiconductor metrology equipment. The test structure may include patterned chromium features that protrude vertically from a thin-film gold surface deposited onto a fused silica substrate.

Inventors

  • Michael A. Huff

Assignees

  • CORPORATION FOR NATIONAL RESEARCH INITIATIVES

Dates

Publication Date
20260505
Application Date
20211216

Claims (9)

  1. 1 . A method for making one or more test structures suitable for characterizing and calibrating semiconductor metrology equipment, wherein the one or more test structures are fabricated by: selecting a suitable first substrate; performing a cleaning process on the first substrate to remove residues and contaminates from the surfaces of the first substrate; depositing a first layer of gold using physical vapor deposition onto a surface of the first substrate; dehydrating the first substrate; after dehydrating the first substrate, vapor depositing a monolayer of hexamethyldisilazane (HMDS) onto the first layer of gold; after deposing the monolayer of HMDS, depositing a second layer of photoresist sensitive to e-beam lithography radiation by spin casting onto the monolayer of HMDS on the first layer of gold; depositing a third layer of gold using physical vapor deposition onto a top surface of the second layer of photoresist; performing electron-beam exposure lithography onto the second layer of photoresist to transfer a test structure design layout to the second layer of photoresist; performing a post-exposure bake on the second layer of photoresist; removing the third layer of gold deposited on top of the second layer of photoresist; performing development of the second layer of photoresist to pattern the second layer of photoresist; depositing a thin-film fourth layer of chromium onto the first substrate using physical vapor deposition whereby the fourth layer of chromium is deposited onto the second layer of photoresist where the second layer of photoresist remains after development and whereby the fourth layer of chromium is deposited directly onto the first layer of gold deposited onto the surface of the first substrate; performing lift-off patterning of the fourth layer of chromium by removing the patterned second layer of photoresist thereby leaving the fourth layer of chromium only on those areas on the first layer of the gold where the second layer of photoresist was removed by development to provide a plurality of patterned chromium features; and dicing the first substrate into plurality of die, each die of the plurality of die including patterned chromium features that protrude vertically from the first layer of the gold.
  2. 2 . The method of claim 1 , wherein the first substrate is made of fused silica.
  3. 3 . The method of claim 1 , wherein the first layer of gold has a thickness of 40 nanometers.
  4. 4 . The method of claim 1 , wherein the second layer of photoresist is of a negative polarity type.
  5. 5 . The method of claim 1 , wherein the third layer of gold has a thickness of 40 nanometers.
  6. 6 . The method of claim 1 , wherein the fourth layer of chromium has a thickness of 100 nanometers.
  7. 7 . The method of claim 1 , where the second layer of photoresist has a thickness of more than 100 nanometers.
  8. 8 . The method of claim 1 , wherein the patterned chromium features include zigzag lines and a plurality of rectangles spaced in regular intervals.
  9. 9 . The method of claim 1 , wherein the patterned chromium features include lines that zig-zag in one or both directions with a 90-degree angle between zig elements and zag elements of the zig-zag.

Description

FIELD OF INVENTION The present invention is directed to the fabrication and manufacturing of test structures and more particularly to the fabrication and manufacturing of test structures made using e-beam lithography that are employed for quality control and characterization of metrology equipment used in semiconductor manufacturing. BACKGROUND A processing step is the most fundamental element for the fabrication of microsystems and is usually, but not always, performed on a single item of equipment. There are a number of types of processing steps with the most general types including: thin-film depositions; etching; photolithography; planarization; introduction of dopants; and so on. A process sequence can be used at various levels of maturity of the microsystems manufacturing, ranging from the initial process sequence development to something that has been sufficiently developed to the point where working devices can be reliably manufactured. SUMMARY OF INVENTION The present invention relates to metrology techniques used to measure and characterize features made on semiconductor surfaces. Specifically, the manufacturing of test structures that can be used to characterize and maintain quality control of the metrology tools used in semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an illustration of the fabrication of microsystems devices using semiconductor manufacturing methods. FIGS. 2A-2H illustrate a series of processing steps in the process sequence for manufacturing the test structures disclosed in the present invention. FIG. 3 is the design layout of the test structures for a single die. FIG. 4 is a magnified portion of the test structure pattern focusing on the zig-zag pattern. FIG. 5 is a magnified portion of the test structure pattern focusing on the array of small rectangular features. FIG. 6 is an even more magnified portion of the test structure pattern focusing on the array of rectangular features. FIG. 7 illustrates a method for making test structures suitable for characterizing and calibrating semiconductor metrology equipment according to an example of the present technology. DETAILED DESCRIPTION OF THE INVENTION Herein, and throughout this disclosure, micro- and nanosystems is defined as devices made using semiconductor manufacturing methods for the implementation of integrated circuits whether digital, analog or both (i.e., mixed signal circuits); micro-electro-mechanical systems (MEMS); photonics; nano-electro-mechanical systems (NEMS); vacuum electronics; compound semiconductor devices and systems; nanotechnology; and any technology using or partly using semiconductor fabrication methods. To avoid needless repetition, throughout this disclosure the term microsystems will be used as the label for both microsystems and nanosystems since these technologies use the same fabrication methods. Semiconductor manufacturing for the production of micro- and nanosystems is an advanced and rapidly changing industry. Most micro- and nanosystems are made what is called a process sequence. A process sequence is defined as a grouping of processing steps that have been assembled into an ordered, sequentially-performed sequence of procedures that are performed on a substrate or set of substrates, which are sufficient to result in functional devices. A processing step is defined as a single process operation that is performed on a substrate or a set of substrates in order to advance the fabrication of devices, but is not sufficient to result in the complete implementation of functional devices. As discussed above, a processing step is the most fundamental element for the fabrication of microsystems and is usually, but not always, performed on a single item of equipment. There are a number of types of processing steps with the most general types including: thin-film depositions; etching; photolithography; planarization; introduction of dopants; and so on. A process sequence can be used at various levels of maturity of the microsystems manufacturing, ranging from the initial process sequence development to something that has been sufficiently developed to the point where working devices can be reliably manufactured. Some of the major categories of processing step types used in process sequences includes (see FIG. 1): thin film depositions or growths; lithography; etching; impurity doping; and metrology. Additionally, depending on the IC process sequence involved, there may be other types of processes in the sequence as well such as planarization, rapid thermal anneals, cleans, and others. That is, there are other processing steps that can also be used not shown in FIG. 1, particularly more specified device production, but the actual processing steps included in a process sequence is not important to the present disclosure. The important point of FIG. 1 is that metrology is an essential element of most process sequences and are performed at various stages of the process sequence to mon