US-12619203-B2 - Switch switching method and related apparatus

US12619203B2US 12619203 B2US12619203 B2US 12619203B2US-12619203-B2

Abstract

A switch switching method and a related apparatus. The method includes: receiving, by an MIPI switch, an MIPI instruction, and parsing the MIPI instruction preliminarily, to obtain an address and a control instruction in the MIPI instruction; determining, by the MIPI switch, whether the address in the MIPI instruction is the same as an address of the MIPI switch; if the addresses are the same, writing the control instruction into a data register of the MIPI switch; transmitting, by the MIPI switch, the control instruction in the data register of the MIPI switch to a mode identification module; determining, by the mode identification module, which control instruction bits control the MIPI switch, and sending these control instruction bits to a translator in the MIPI switch; and translating, by the translator in the MIPI switch, the control instruction into a component status.

Inventors

Dan Chen
Cheng Jiang

Assignees

HONOR DEVICE CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20220412
Priority Date: 20210611

Claims (17)

1 . A mobile industry processor interface (MIPI) switch, comprising: a pin module comprising a first pin; a sub-switch module comprising at least one sub-switch; and a controller, configured to: receive an MIPI instruction that comprises a control instruction and address bit, wherein the address bit is configured to represent address information of the MIPI instruction; determine a Y-bit instruction in the control instruction based on a status of the first pin when the address information included in the MIPI instruction is configured to control the same address information as the MIPI switch, wherein the control instruction comprises an X-bit instruction, and wherein Y is less than or equal to X; and switch the at least one sub-switch based on the Y-bit instruction, wherein the controller comprises: an address register configured to store a first MIPI address, wherein the MIPI instruction comprises a second MIPI address; a decoder configured to: parse the MIPI instruction to obtain the second MIPI address and the control instruction; and determine whether the first MIPI address is the same as the second MIPI address; a data register configured to store the control instruction; and a mode identification module configured to determine the Y-bit instruction in the control instruction based on the status of the first pin when the first MIPI address is the same as the second MIPI address.
2 . The MIPI switch of claim 1 , wherein the Y-bit instruction is a first Y-bit instruction, wherein the control instruction includes a second Y-bit instruction, and wherein the second Y-bit instruction is configured to switch a sub-switch of another MIPI switch.
3 . The MIPI switch of claim 1 , wherein the first pin has N statuses, and wherein when being configured to determine the Y-bit instruction in the control instruction based on the status of the first pin, the mode identification module is configured to determine, based on first control logic, the Y-bit instruction that is in the control instruction and that is corresponding to the status of the first pin, wherein the first control logic comprises correspondences between the N statuses and Y-bit instructions, and wherein different statuses correspond to different Y-bit instructions in the control instruction.
4 . The MIPI switch of claim 3 , wherein a K-bit instruction in the Y-bit instruction is a flag bit instruction, wherein K is a positive integer greater than or equal to 1 and less than or equal to X, and wherein the controller further comprises a translator configured to switch the at least one sub-switch based on the Y-bit instruction by: skipping responding to the Y-bit instruction if the flag bit instruction indicates a first state; and responding to the Y-bit instruction if the flag bit instruction indicates a second state.
5 . The MIPI switch of claim 4 , further comprising general-purpose input/output (GPIO) pins, wherein at least one of the GPIO pins is connected to a GPIO switch, wherein different GPIO pins are connected to different GPIO switches, and wherein the translator is further configured to: determine, based on second control logic, a Z-bit instruction that is in the control instruction and that is corresponding to the GPIO pins, wherein the second control logic comprises correspondences between the GPIO pins and Z-bit instructions, wherein different GPIO pins correspond to different Z-bit instructions in the control instruction, and wherein Z is less than or equal to X; and switch the GPIO switch based on the Z-bit instruction.
6 . The MIPI switch of claim 5 , wherein the Y-bit instruction is a first Y-bit instruction, wherein the control instruction includes a second Y-bit instruction, and wherein the second Y-bit instruction is configured to switch a sub-switch of another MIPI switch.
7 . A switch switching method, implemented by a mobile industry processor interface (MIPI) switch comprising a pin module comprising a first pin and a sub-switch module comprising at least one sub-switch, wherein the method comprises: receiving an MIPI instruction comprising a control instruction; determining a Y-bit instruction in the control instruction based on a status of the first pin when it is determined that the MIPI instruction is configured to control the MIPI switch, wherein the control instruction comprises an X-bit instruction, and wherein Y is less than or equal to X, wherein the MIPI switch corresponds to a first MIPI address, wherein the MIPI instruction comprises a second MIPI address, and wherein determining the Y-bit instruction in the control instruction further comprises: parsing the MIPI instruction to obtain the second MIPI address and the control instruction; determining whether the first MIPI address is the same as the second MIPI address; and determining the Y-bit instruction in the control instruction based on the status of the first pin if the first MIPI address is the same as the second MIPI address; and switching the at least one sub-switch based on the Y-bit instruction.
8 . The method of claim 7 , wherein the Y-bit instruction is a first Y-bit instruction, wherein the control instruction includes a second Y-bit instruction, and wherein the method further comprises switching a sub-switch of another MIPI switch based on the second Y-bit instruction.
9 . The method of claim 7 , wherein the first pin has N statuses, and wherein determining the Y-bit instruction in the control instruction based on the status of the first pin comprises determining, based on first control logic, the Y-bit instruction that is in the control instruction and that is corresponding to the status of the first pin, wherein the first control logic comprises correspondences between the N statuses and Y-bit instructions, and wherein different connection statuses correspond to different Y-bit instructions in the control instruction.
10 . The method of claim 9 , wherein a K-bit instruction in the Y-bit instruction is a flag bit instruction, wherein K is a positive integer greater than or equal to 1 and less than or equal to X, and wherein switching the at least one sub-switch based on the Y-bit instruction comprises: skipping responding to the Y-bit instruction if the flag bit instruction indicates a first state; and responding to the Y-bit instruction if the flag bit instruction indicates a second state.
11 . The method of claim 10 , wherein the MIPI switch further comprises general-purpose input/output (GPIO) pins, wherein at least one of the GPIO pins in the MIPI switch is connected to a GPIO switch, wherein different GPIO pins are connected to different GPIO switches, and wherein the method further comprises: determining, based on second control logic, a Z-bit instruction that is in the control instruction and that is corresponding to the GPIO pins, wherein the second control logic comprises correspondences between the GPIO pins and Z-bit instructions, wherein different GPIO pins correspond to different Z-bit instructions in the control instruction, and wherein Z is less than or equal to X; and switching the GPIO switch based on the Z-bit instruction.
12 . The method of claim 11 , wherein the Y-bit instruction is a first Y-bit instruction, wherein the control instruction includes a second Y-bit instruction, and wherein the method further comprises switching a sub-switch of another MIPI switch based on the second Y-bit instruction.
13 . An electronic device, comprising: an antenna; and a mobile industry processor interface (MIPI) switch, comprising: a pin module comprising a first pin; a sub-switch module comprising at least one sub-switch coupled to the antenna; and a controller, configured to: receive an MIPI instruction that comprises a control instruction and address bit, wherein the address bit is configured to represent address information of the MIPI instruction; determine a Y-bit instruction in the control instruction based on a status of the first pin when the address information included in the MIPI instruction is configured to control the same address information as the MIPI switch, wherein the Y-bit instruction is a first Y-bit instruction, wherein the control instruction comprises an X-bit instruction, wherein Y is less than or equal to X, wherein the control instruction includes a second Y-bit instruction, and wherein the second Y-bit instruction is configured to switch a sub-switch of another MIPI switch; and switch the at least one sub-switch based on the Y-bit instruction.
14 . The electronic device of claim 13 , wherein the controller comprises: an address register configured to store a first MIPI address, wherein the MIPI instruction comprises a second MIPI address; a decoder configured to: parse the MIPI instruction to obtain the second MIPI address and the control instruction; and determine whether the first MIPI address is the same as the second MIPI address; a data register configured to store the control instruction; and a mode identification module configured to determine the Y-bit instruction in the control instruction based on the status of the first pin when the first MIPI address is the same as the second MIPI address.
15 . The electronic device of claim 14 , wherein the first pin has N statuses, and wherein when being configured to determine the Y-bit instruction in the control instruction based on the status of the first pin, the mode identification module is configured to determine, based on first control logic, the Y-bit instruction that is in the control instruction and that is corresponding to the status of the first pin, wherein the first control logic comprises correspondences between the N statuses and Y-bit instructions, and wherein different statuses correspond to different Y-bit instructions in the control instruction.
16 . The electronic device of claim 15 , wherein a K-bit instruction in the Y-bit instruction is a flag bit instruction, wherein K is a positive integer greater than or equal to 1 and less than or equal to X, and wherein the controller further comprises a translator configured to switch the at least one sub-switch based on the Y-bit instruction by: skipping responding to the Y-bit instruction if the flag bit instruction indicates a first state; and responding to the Y-bit instruction if the flag bit instruction indicates a second state.
17 . The electronic device of claim 16 , wherein the MIPI switch further comprises general-purpose input/output (GPIO) pins, wherein at least one of the GPIO pins is connected to a GPIO switch, wherein different GPIO pins are connected to different GPIO switches, and wherein the translator is further configured to: determine, based on second control logic, a Z-bit instruction that is in the control instruction and that is corresponding to the GPIO pins, wherein the second control logic comprises correspondences between the GPIO pins and Z-bit instructions, wherein different GPIO pins correspond to different Z-bit instructions in the control instruction, and wherein Z is less than or equal to X; and switch the GPIO switch based on the Z-bit instruction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a U.S. National Stage of International Application No. PCT/CN2022/086439 filed on Apr. 12, 2022, which claims priority to Chinese Patent Application No. 202110654892.7, filed with the China National Intellectual Property Administration on Jun. 11, 2021, both of which are incorporated herein by reference in their entireties. TECHNICAL FIELD This solution relates to the field of radio frequency technologies, and in particular, to a switch switching method and a related apparatus. BACKGROUND With continuous development of technologies, increasing of a quantity of antennas day by day requires more and more switching statuses. Thus, a quantity of antenna switches also increases. In the conventional technology, each switch is assigned one MIPI address, switches receive MIPI instructions in series. This results in a long switch response time. In addition, a platform limits a quantity of MIPI instructions, and one MIPI instruction acts on one switch. This limits a quantity of switches, and severely limits antenna design. Therefore, how to reduce a response time of the switch and overcome a limitation of the platform on the quantity of switches is a problem to be resolved urgently at present. SUMMARY This application provides a switch switching method and a related apparatus, so that a plurality of MIPI switches can share one MIPI address, that is, one MIPI instruction controls a plurality of MIPI switches. This not only overcomes a limitation of a platform on a quantity of MIPI switches, but also reduces response time of the MIPI switch and a switching latency of the MIPI switch. According to a first aspect, this application provides a switch switching method, and the method may be applied to a mobile industry processor interface MIPI switch. In this method, the MIPI switch can receive an MIPI instruction. The MIPI switch may include a first pin. The MIPI instruction may include a control instruction. The MIPI switch may determine a Y-bit instruction in the control instruction based on a status of the first pin when determining that the MIPI instruction is used to control the MIPI switch. The control instruction includes an X-bit instruction, where Y is less than or equal to X. The MIPI switch switches based on the Y-bit instruction. In the solution provided in this application, the MIPI switch may determine, based on the status of the first pin included in the MIPI switch, which part of the control instruction is to be responded, that is, the Y-bit instruction mentioned in the foregoing method. It may be understood that a translator in the MIPI switch may translate the Y-bit instruction into a component status, that is, control turn-off and turn-on of a sub-switch of the MIPI switch. It should be noted that based on the foregoing method, one MIPI instruction may include different Y-bit instructions. Therefore, one MIPI instruction can be used to control a plurality of MIPI switches. In this method, a switching latency of the MIPI switch can be reduced, so that the MIPI switch responds in a timely manner, and a limitation of a platform on a quantity of MIPI switches can be overcome. With reference to the first aspect, in a possible implementation, the MIPI switch corresponds to a first MIPI address, and the MIPI instruction includes a second MIPI address. Before that the MIPI switch determines a Y-bit instruction in the control instruction based on a status of the first pin when determining that the MIPI instruction is used to control the MIPI switch, the switch switching method may further include: The MIPI switch parses the MIPI instruction, to obtain the second MIPI address and the control instruction. That the MIPI switch determines a Y-bit instruction in the control instruction based on a status of the first pin when determining that the MIPI instruction is used to control the MIPI switch may specifically include: The MIPI switch determines whether the first MIPI address is the same as the second MIPI address; and if the first MIPI address is the same as the second MIPI address, the MIPI switch determines the Y-bit instruction in the control instruction based on the status of the first pin. In the solution provided in this application, before the Y-bit instruction responded by the MIPI switch are determined, it needs to be determined whether an address of the MIPI switch is the same as an address in the MIPI instruction. If the address of the MIPI switch is the same as the address in the MIPI instruction, the Y-bit instruction responded by the MIPI switch may be determined based on the status of the first pin, so that the MIPI switch can successfully respond to a corresponding MIPI instruction. With reference to the first aspect, in a possible implementation, the first pin has N statuses. That the MIPI switch may determine a Y-bit instruction in the control instruction based on a status of the first pin specifically includes: The MIPI switch may deter