US-12619270-B2 - Hybrid LDO regulator including analog LDO regulator and digital LDO regulator

Abstract

A hybrid low drop-out (LDO) regulator is provided. The hybrid LDO regulator provides current to a load block, and includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information indicating the peak current is consumed.

Inventors

• Jaehoon Lee
• Yelim YOUN
• Yong Lim

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20230130

Priority Date

20220310

Claims (20)

1. 1 . A hybrid low drop-out (LDO) regulator which provides current to a load block, comprising: an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information received from the load block indicating the peak current is consumed.
2. 2 . The hybrid LDO regulator of claim 1 , wherein the digital LDO regulator comprises: a pass transistor array comprising a plurality of pass transistors; and a controller configured to control at least one of the plurality of pass transistors to turn on in synchronization with a clock signal received from the load block, wherein the clock signal toggles to indicate the peak current is consumed in the load block.
3. 3 . The hybrid LDO regulator of claim 2 , wherein the pass transistor array further comprises a plurality of NAND gates respectively corresponding to the plurality of pass transistors, and wherein each of the plurality of NAND gates is configured to provide an output signal to a gate of a corresponding pass transistor, from among the plurality of pass transistors, based on the clock signal and a control code.
4. 4 . The hybrid LDO regulator of claim 3 , wherein the digital LDO regulator comprises a level shifter configured to generate the control code, and generate the control code in synchronization with the clock signal.
5. 5 . The hybrid LDO regulator of claim 2 , wherein the digital LDO regulator further comprises a comparator configured to generate a selection signal based on a feedback voltage and a reference voltage, and wherein the controller is further configured to control a number of transistors among the plurality of pass transistors that are turned on based on the selection signal.
6. 6 . The hybrid LDO regulator of claim 5 , wherein the digital LDO regulator further comprises a clock generator configured to generate a comparison clock signal based on the clock signal, and wherein the comparator further is configured to generate the selection signal in synchronization with the comparison clock signal.
7. 7 . The hybrid LDO regulator of claim 2 , wherein the controller is further configured to control the pass transistor array to perform a coarse search operation in which at least two pass transistors among the plurality of pass transistors are turned on simultaneously.
8. 8 . The hybrid LDO regulator of claim 7 , wherein the digital LDO regulator further comprises a comparator configured to generate a selection signal based on a feedback voltage and a reference voltage, and wherein the controller is further configured to repeatedly perform the coarse search operation until a voltage level of the feedback voltage becomes lower than a voltage level of the reference voltage.
9. 9 . The hybrid LDO regulator of claim 8 , wherein the controller is further configured to repeatedly perform a fine search operation in which individual pass transistors, among the plurality of pass transistors, are turned on one by one.
10. 10 . The hybrid LDO regulator of claim 9 , wherein the controller is further configured to maintain a state of the plurality of pass transistors based on a change in a voltage level of the selection signal.
11. 11 . The hybrid LDO regulator of claim 2 , wherein the plurality of pass transistors comprises at least one large power transistor and at least one small power transistor, and wherein the controller is further configured to turn on the at least one large power transistor before the at least one small power transistor.
12. 12 . The hybrid LDO regulator of claim 1 , wherein the analog LDO regulator comprises: a voltage divider configured to generate a feedback voltage based on an output voltage at an output voltage terminal; an amplifier configured to receive the feedback voltage and a reference voltage; and a pass transistor connected between a power supply voltage and the voltage divider, and configured to be turned on and off based on an output of the amplifier.
13. 13 . The hybrid LDO regulator of claim 12 , further comprising a decoupling capacitor connected to the output voltage terminal.
14. 14 . A hybrid low drop-out (LDO) regulator comprising: an analog LDO regulator configured to provide a first current corresponding to an average current consumed in a plurality of load blocks; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by a load block, from among the plurality of load blocks, consuming the peak current based on information received from the load block indicating the peak current is consumed.
15. 15 . The hybrid LDO regulator of claim 14 , wherein the digital LDO regulator comprises: a pass transistor array comprising a plurality of pass transistors; and a controller configured to control at least one of the plurality of pass transistors to turn on in synchronization with a clock signal received from the load block, wherein the clock signal toggles to indicate the peak current is consumed in the load block.
16. 16 . The hybrid LDO regulator of claim 15 , wherein the pass transistor array further comprises a plurality of NAND gates respectively corresponding to the plurality of pass transistors, and wherein each of the plurality of NAND gates is configured to provide an output signal to a gate of a corresponding pass transistor, from among the plurality of pass transistors, based on the clock signal and a control code.
17. 17 . The hybrid LDO regulator of claim 15 , wherein the controller is further configured to control at least two pass transistors among the plurality of pass transistors to simultaneously turn on, based on the clock signal.
18. 18 . A user device comprising: an application processor comprising at least one hybrid low drop-out (LDO) regulator; and a power management integrated circuit configured to provide power to the application processor, wherein the at least one hybrid LDO regulator comprises: an analog LDO regulator configured to provide a first current corresponding to an average current consumed in a load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information received from the load block indicating the peak current is consumed.
19. 19 . The user device of claim 18 , wherein the digital LDO regulator comprises: a pass transistor array comprising a plurality of pass transistors; and a controller configured to control at least one of the plurality of pass transistors to turn on in synchronization with a clock signal received from the load block, wherein the clock signal toggles to indicate the peak current is consumed in the load block.
20. 20 . The user device of claim 19 , wherein the controller is further configured to control at least two pass transistors among the plurality of pass transistors to simultaneously turn on, based on the clock signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0029895, filed on Mar. 10, 2022, and Korean Patent Application No. 10-2022-0079054, filed on Jun. 28, 2022, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND The present disclosure relate to a low drop-out (LDO) regulator. A voltage regulator is used to provide a uniform voltage to a circuit. The voltage regulator may be classified as a linear regulator and a switching regulator according to a voltage regulation method. The switching regulator has good efficiency, but has a disadvantage in that noise characteristics are poor. In contrast, the linear regulator has low efficiency but has an advantage in that noise characteristics are good. Because the linear regulator has good noise characteristics, it can supply a precise and stable voltage. An LDO regulator is a type of linear regulator, and may be used to reliably supply power to various types of electronic devices. For example, the LDO regulator may be used in a power management integrated circuit (PMIC) of a mobile device such as a smart phone or a tablet PC. Among the LDO regulators, an analog LDO regulator may be used. However, in the case of a related analog LDO regulator, the required current cannot be accurately supplied to a load block that consumes a spike current or a peak current, resulting in large fluctuations in the output voltage. Therefore, the related analog LDO regulator requires a large-capacity decoupling capacitor to reduce fluctuations in the output voltage, which is a major obstacle in designing the LDO regulator having a small size. SUMMARY Embodiments of the present disclosure provide a hybrid LDO regulator that can be implemented in a small area while minimizing the fluctuation of the output voltage. According to an aspect of an example embodiment, a hybrid low drop-out (LDO) regulator provides current to a load block, and includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information indicating the peak current is consumed. According to an aspect of an example embodiment, a hybrid LDO regulator includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed in a plurality of load blocks; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by a load block, from among the plurality of load blocks, consuming the peak current based on information indicating the peak current is consumed. According to an aspect of an example embodiment, an application processor includes at least one hybrid LDO regulator; and a power management integrated circuit configured to provide power to the application processor. The at least one hybrid LDO regulator includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed in a load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information indicating the peak current is consumed. BRIEF DESCRIPTION OF THE FIGURES The above and other aspects and features of the present disclosure will be more clearly understood from the following description of example embodiments, taken in conjunction with the accompanying drawings, in which: embodiment; FIG. 1 is a block diagram illustrating a user device, according to an example FIG. 2 is a diagram illustrating an analog LDO regulator; FIGS. 3A and 3B are diagrams for describing a fluctuation of an output voltage according to a sampling speed; FIG. 4 is a block diagram illustrating a hybrid LDO regulator, according to an example embodiment; FIG. 5 is a diagram illustrating an example operation of a hybrid LDO regulator, according to an example embodiment; FIG. 6 is a circuit diagram illustrating a hybrid LDO regulator, according to an example embodiment; FIG. 7 is a timing diagram illustrating operation of a digital LDO regulator, according to an example embodiment; FIG. 8 is a diagram illustrating a pass transistor array of a digital LDO regulator supporting coarse search and fine search operations, according to an example embodiment; FIG. 9 is a timing diagram illustrating coarse search and fine search operations, according to an example embodiment; FIG. 10 is a diagram illustrating a digital LDO regulator, according to an example embodiment; and FIGS. 11 and 12 are block diagrams illustrating a hybrid LDO regulator according to an example embodiment. DETAILED DESCRIPTION Hereinafter, example embodiments will be described with reference to the accompanying drawings. FIG. 1 is a blo