US-12619272-B2 - Reference voltage generation device

US12619272B2US 12619272 B2US12619272 B2US 12619272B2US-12619272-B2

Abstract

The present invention provides a reference voltage generation device which includes a constant current circuit outputting a constant current in response to an input voltage; a voltage generation circuit connected in series to the constant current circuit, using the constant current as an input current, and generating an output voltage based on the input current; and a reference voltage output port outputting the output voltage. In the constant current circuit, multiple depletion type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the constant current circuit. In the voltage generation circuit, multiple enhancement type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the voltage generation circuit.

Inventors

Satoshi Suzuki

Assignees

ABLIC INC.

Dates

Publication Date: 20260505
Application Date: 20240326
Priority Date: 20230331

Claims (3)

1 . A reference voltage generation device, comprising: a constant current circuit which outputs a constant current in response to an input voltage; a voltage generation circuit which is connected in series to the constant current circuit, uses the constant current as an input current, and generates an output voltage based on the input current; and a reference voltage output port which outputs the output voltage, wherein the constant current circuit comprises a depletion type MOS transistor circuit, and the depletion type MOS transistor circuit has a depletion type MOS transistor circuit total gate width and a depletion type MOS transistor circuit total gate length, the depletion type MOS transistor circuit comprises n (n is an integer 2, 3, 4 . . . ) depletion type MOS transistors, the n depletion type MOS transistors, from a first depletion type MOS transistor to an n th depletion type MOS transistor, are connected in series, the first depletion type MOS transistor has a first gate width and a first gate length, and has a gate and a source connected, the n th depletion type MOS transistor has the first gate width and an n th gate length, and has a drain connected to the input voltage, the voltage generation circuit comprises an enhancement type MOS transistor circuit, and the enhancement type MOS transistor circuit has an enhancement type MOS transistor circuit total gate width and an enhancement type MOS transistor circuit total gate length, the enhancement type MOS transistor circuit comprises m (m is an integer 2, 3, 4 . . . ) enhancement type MOS transistors, the m enhancement type MOS transistors, from a first enhancement type MOS transistor to an m th enhancement type MOS transistor, are connected in series, the first enhancement type MOS transistor has the first gate width and a gate length of the first enhancement type MOS transistor, and has a drain and a gate connected, the m th enhancement type MOS transistor has the first gate width and a gate length of the m th enhancement type MOS transistor, the source of the first depletion type MOS transistor and the drain of the first enhancement type MOS transistor are connected to the reference voltage output port, the first gate width is the depletion type MOS transistor circuit total gate width and the enhancement type MOS transistor circuit total gate width, a sum of the first gate length to the n th gate length is the depletion type MOS transistor circuit total gate length, a sum of the gate length of the first enhancement type MOS transistor to the gate length of the m th enhancement type MOS transistor is the enhancement type MOS transistor circuit total gate length; and wherein the first gate width is 5 μm or less, the first gate length and the n th gate length of the depletion type MOS transistor are 25 μm or less respectively, and the gate length of the first enhancement type MOS transistor and the gate length of the m th enhancement type MOS transistor are 25 μm or less respectively.
2 . A reference voltage generation device, comprising: a constant current circuit which outputs a constant current in response to an input voltage; a voltage generation circuit which is connected in series to the constant current circuit, uses the constant current as an input current, and generates an output voltage based on the input current; and a reference voltage output port which outputs the output voltage, wherein the constant current circuit comprises a depletion type MOS transistor circuit, and the depletion type MOS transistor circuit has a depletion type MOS transistor circuit total gate width and a depletion type MOS transistor circuit total gate length, the depletion type MOS transistor circuit comprises n (n is an integer 2, 3, 4 . . . )×p(p is an integer 2, 3, 4 . . . ) depletion type MOS transistors, the n depletion type MOS transistors, from a first depletion type MOS transistor to an n th depletion type MOS transistor, in a first column are connected in series, the first depletion type MOS transistor has a first gate width and a first gate length, and has a gate and a source connected, the n th depletion type MOS transistor has the first gate width and an n th gate length, and has a drain connected to the input voltage, n depletion type MOS transistors from a first depletion type MOS transistor to an n th depletion type MOS transistor in a p th column are connected in series, and the depletion type MOS transistors are arranged in parallel from the first column to the p th column, the first depletion type MOS transistor in the p th column has a p th gate width and the first gate length, and has a gate and a source connected, the n th depletion type MOS transistor in the p th column has the p th gate width and the n th gate length, and has a drain connected to the input voltage, the voltage generation circuit comprises an enhancement type MOS transistor circuit, and the enhancement type MOS transistor circuit has an enhancement type MOS transistor circuit total gate width and an enhancement type MOS transistor circuit total gate length, the enhancement type MOS transistor circuit comprises m (m is an integer 2, 3, 4 . . . ) x p (p is an integer 2, 3, 4 . . . ) enhancement type MOS transistors, the m enhancement type MOS transistors, from a first enhancement type MOS transistor to an m th enhancement type MOS transistor, in a first column are connected in series, the first enhancement type MOS transistor has the first gate width and a gate length of the first enhancement type MOS transistor, and has a drain and a gate connected, the m th enhancement type MOS transistor has the first gate width and a gate length of the m th enhancement type MOS transistor, m enhancement type MOS transistors from a first enhancement type MOS transistor in a p th column to an m th enhancement type MOS transistor are connected in series, and the enhancement type MOS transistors are arranged in parallel from the first column to the p th column, the first enhancement type MOS transistor in the p th column has the p th gate width and the first gate length, and has a gate and a source connected, the source of the first depletion type MOS transistor in the first column, the drain of the first enhancement type MOS transistor in the first column, a source of the first depletion type MOS transistor in the p th column, and a drain of the first enhancement type MOS transistor in the p th column are connected to the reference voltage output port, a sum of the first gate width to the p th gate width is the depletion type MOS transistor circuit total gate width and the enhancement type MOS transistor circuit total gate width, a sum of the first gate length to the n th gate length is the depletion type MOS transistor circuit total gate length, and a sum of the gate length of the first enhancement type MOS transistor to the gate length of the m th enhancement type MOS transistor is the enhancement type MOS transistor circuit total gate length.
3 . The reference voltage generation device according to claim 2 , wherein the first gate width and the p th gate width are 5 μm or less respectively, the first gate length and the n th gate length of the depletion type MOS transistor are 25 μm or less respectively, and the first gate length and the m th gate length of the enhancement type MOS transistor are 25 μm or less respectively.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefits of Japanese application no. 2023-057979, filed on Mar. 31, 2023, and Japanese application no. 2024-012112, filed on Jan. 30, 2024. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. BACKGROUND Technical Field The present invention relates to a reference voltage generation device. Description of Related Art Reference voltage circuits, which are often used in analog processing circuits, are required to output a reference voltage with high stability and have low current consumption. However, the purpose of the related art is to improve the yield by compensating for the temperature characteristics and correcting the manufacturing process variations. In order to reduce current consumption, generally, the channel length of the transistors which constitute the reference voltage circuit is increased to suppress the drain current. However, there is a problem that, in the case where the channel length is increased, the electrical characteristics thereof are more likely to be affected by external stress other than the semiconductor chip, such as shrinkage of the resin in the resin sealing formation process in the post-process, which causes the stability of the reference voltage to decrease. SUMMARY The present invention provides a reference voltage generation device, including: a constant current circuit which outputs a constant current in response to an input voltage; a voltage generation circuit which is connected in series to the constant current circuit, uses the constant current as an input current, and generates an output voltage based on the input current; and a reference voltage output port which outputs the output voltage, in which the constant current circuit includes a depletion type MOS transistor circuit, and the depletion type MOS transistor circuit has a depletion type MOS transistor circuit total gate width and a depletion type MOS transistor circuit total gate length,the depletion type MOS transistor circuit includes n (n is an integer 2, 3, 4 . . . ) depletion type MOS transistors,the n depletion type MOS transistors, from a first depletion type MOS transistor to an nth depletion type MOS transistor, are connected in series,the first depletion type MOS transistor has a first gate width and a first gate length, and has a gate and a source connected,the nth depletion type MOS transistor has the first gate width and an nth gate length, and has a drain connected to the input voltage,the voltage generation circuit includes an enhancement type MOS transistor circuit, and the enhancement type MOS transistor circuit has an enhancement type MOS transistor circuit total gate width and an enhancement type MOS transistor circuit total gate length,the enhancement type MOS transistor circuit includes m (m is an integer 2, 3, 4 . . . ) enhancement type MOS transistors,the m enhancement type MOS transistors, from a first enhancement type MOS transistor to an mth enhancement type MOS transistor, are connected in series,the first enhancement type MOS transistor has the first gate width and an E1th gate length, and has a drain and a gate connected,the mth enhancement type MOS transistor has the first gate width and an E1th gate length,the source of the first depletion type MOS transistor and the drain of the first enhancement type MOS transistor are connected to the reference voltage output port,the first gate width is the depletion type MOS transistor circuit total gate width and the enhancement type MOS transistor circuit total gate width,a sum of the first gate length to the nth gate length is the depletion type MOS transistor circuit total gate length, anda sum of the E1th gate length to the E1th gate length is the enhancement type MOS transistor circuit total gate length. The present invention provides a reference voltage generation device which suppresses current consumption and the influence of external stress. Problems, configurations, and effects other than those described above will be made clear by the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating the reference voltage generation device according to the first embodiment (n=n, m=m) of the present invention. FIG. 2 is a circuit diagram illustrating the reference voltage generation device according to a modified example of the first embodiment (n=n, m=m) of the present invention. FIG. 3 is a circuit diagram illustrating the reference voltage generation device according to the first embodiment (n=2, m=2) of the present invention. FIG. 4 is a circuit diagram illustrating the reference voltage generation device according to the second embodiment (n=n, m=m, p=p) of the present invention. FIG. 5 is a circuit diagram illustrating the reference voltage generation device according to a modified example of the second embodiment (n=