US-12619273-B2 - Simplified clocking and input/output timing using single data rate link for multiple system-on-chip device

Abstract

In some aspects, an electronic device may include a first system-on-chip (SOC) to generate peripheral data and a single data rate (SDR) clock signal to transport to a second SOC connected to the first SOC by a SoundWire bridge having a single clock line. The electronic device may transport the peripheral data to the second SOC over the SoundWire bridge according to the SDR clock signal carried on the single clock line. For example, to transport the peripheral data to the second SOC over the SoundWire bridge, the first SOC may drive the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal, and the second SOC may sample the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal. Numerous other aspects are described.

Inventors

• Syed Naseef
• Lior Amarilio

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260505

Application Date

20240619

Claims (20)

1. 1 . A method performed by an electronic device, comprising: generating, by a first system-on-chip (SOC), peripheral data and a single data rate (SDR) clock signal to transport to a second SOC connected to the first SOC by a SoundWire bridge having a single clock line to carry the SDR clock signal; and transporting the peripheral data to the second SOC over the SoundWire bridge according to the SDR clock signal carried on the single clock line, wherein transporting the peripheral data to the second SOC over the SoundWire bridge includes: driving, by the first SOC, the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal; and sampling, by the second SOC, the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal.
2. 2 . The method of claim 1 , wherein the one or more drive phases start at rising edges when the SDR clock signal transitions from low to high, and the one or more bus keeper phases start at falling edges when the SDR clock signal transitions from high to low.
3. 3 . The method of claim 1 , wherein the one or more drive phases start at falling edges when the SDR clock signal transitions from high to low, and the one or more bus keeper phases start at rising edges when the SDR clock signal transitions from low to high.
4. 4 . The method of claim 1 , wherein the single clock line occupies one input/output (I/O) pad on the first SOC and one I/O pad on the second SOC.
5. 5 . The method of claim 1 , further comprising: writing a value to a register to initiate a clock stop mechanism that parks the SDR clock signal and a data signal at a low level after a stopping frame.
6. 6 . The method of claim 1 , further comprising: detecting, while the SDR clock signal and a data signal are parked at a low level, wakeup signaling that transitions the data signal to a high level; and restarting the SDR clock signal responsive to detecting the wakeup signaling.
7. 7 . The method of claim 1 , further comprising: resetting registers associated with all peripheral devices connected to the data bus responsive to detecting a sequence of logical values on the data bus over a configured number of successive cycles of the SDR clock signal.
8. 8 . The method of claim 1 , further comprising: delivering, by the second SOC, the peripheral data transported over the SoundWire bridge to one or more peripheral devices connected to the second SOC.
9. 9 . An electronic device, comprising: a first system-on-chip (SOC); a second SOC; and a SoundWire bridge connecting the first SOC to the second SOC, wherein the SoundWire bridge has a single clock line, wherein: the first SOC is configured to generate peripheral data and a single data rate (SDR) clock signal to transport to the second SOC, the first SOC is configured to drive the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal, and the second SOC is configured to sample the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal.
10. 10 . The electronic device of claim 9 , wherein the one or more drive phases start at rising edges when the SDR clock signal transitions from low to high, and the one or more bus keeper phases start at falling edges when the SDR clock signal transitions from high to low.
11. 11 . The electronic device of claim 9 , wherein the one or more drive phases start at falling edges when the SDR clock signal transitions from high to low, and the one or more bus keeper phases start at rising edges when the SDR clock signal transitions from low to high.
12. 12 . The electronic device of claim 9 , wherein the single clock line occupies one input/output (I/O) pad on the first SOC and one I/O pad on the second SOC.
13. 13 . The electronic device of claim 9 , further comprising one or more controllers configured to: write a value to a register to initiate a clock stop mechanism that parks the SDR clock signal and a data signal at a low level after a stopping frame.
14. 14 . The electronic device of claim 9 , further comprising one or more controllers configured to: detect, while the SDR clock signal and a data signal are parked at a low level, wakeup signaling that transitions the data signal to a high level; and restart the SDR clock signal responsive to detecting the wakeup signaling.
15. 15 . The electronic device of claim 9 , further comprising one or more controllers configured to: reset registers associated with all peripheral devices connected to the data bus responsive to detecting a sequence of logical values on the data bus over a configured number of successive cycles of the SDR clock signal.
16. 16 . The electronic device of claim 9 , where the second SOC is further configured to: deliver the peripheral data transported over the SoundWire bridge to one or more peripheral devices connected to the second SOC.
17. 17 . An apparatus, comprising: means for generating peripheral data and a single data rate (SDR) clock signal to transport over a SoundWire bridge having a single clock line; and means for transporting the peripheral data over the SoundWire bridge according to the SDR clock signal carried on the single clock line, wherein the means for transporting the peripheral data over the SoundWire bridge includes: means for driving the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal; and means for sampling the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal.
18. 18 . The apparatus of claim 17 , wherein the one or more drive phases start at rising edges when the SDR clock signal transitions from low to high, and the one or more bus keeper phases start at falling edges when the SDR clock signal transitions from high to low.
19. 19 . The apparatus of claim 17 , wherein the one or more drive phases start at falling edges when the SDR clock signal transitions from high to low, and the one or more bus keeper phases start at rising edges when the SDR clock signal transitions from low to high.
20. 20 . The apparatus of claim 17 , wherein the single clock line occupies one input/output (I/O) pad on a first system-on-chip (SOC) and one I/O pad on a second SOC that are connected via the SoundWire bridge.

Description

FIELD OF THE DISCLOSURE Aspects of the present disclosure generally relate to bridging and specifically relate to techniques, apparatuses, and methods associated with simplified clocking and input/output timing using a single data rate link for a multiple system-on-chip device. BACKGROUND Electronic devices, including mobile communication devices, wearable computing devices such as smartwatches, and/or tablet computers support ever increasing functionalities and capabilities. Many electronic devices include peripheral devices, such as internal microphones and/or speakers, and may include connectors allow the peripheral devices to be used with audiovisual equipment including headphones and/or external speakers, among other examples. In some cases, communication among components of an electronic device may be provided through a digital interface defined by one or more standards, such as the SoundWire standard specified by the Mobile Industry Processor Interface (MIPI) Alliance. For example, the SoundWire standard defines a multi-wire communication bus to facilitate efficient and high-quality audio data transmission between different components within an electronic device. For example, SoundWire supports the transmission of high-resolution audio data to minimize loss of quality during transport, low power consumption that may be important for battery-powered devices, support for multiple channels and various data rates, precise timing and synchronization features to maintain audio quality and mitigate issues such as jitter or latency, and a simplified physical design that reduces the number of required pins and traces on circuit boards to replace older, bulkier interfaces. SUMMARY In some aspects, a method performed by an electronic device includes generating, by a first system-on-chip (SOC), peripheral data and a single data rate (SDR) clock signal to transport to a second SOC connected to the first SOC by a SoundWire bridge having a single clock line to carry the SDR clock signal; and transporting the peripheral data to the second SOC over the SoundWire bridge according to the SDR clock signal carried on the single clock line, wherein transporting the peripheral data to the second SOC over the SoundWire bridge includes: driving, by the first SOC, the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal; and sampling, by the second SOC, the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal. In some aspects, an electronic device includes a first SOC; a second SOC; and a SoundWire bridge connecting the first SOC to the second SOC, wherein the SoundWire bridge has a single clock line, wherein: the first SOC is configured to generate peripheral data and an SDR clock signal to transport to the second SOC, the first SOC is configured to drive the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal, and the second SOC is configured to sample the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal. In some implementations, an apparatus for wireless communication includes means for generating peripheral data and an SDR clock signal to transport over a SoundWire bridge having a single clock line; and means for transporting the peripheral data over the SoundWire bridge according to the SDR clock signal carried on the single clock line, wherein the means for transporting the peripheral data over the SoundWire bridge includes: means for driving the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal; and means for sampling the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal. Aspects of the present disclosure may generally be implemented by or as a method, apparatus, system, computer program product, non-transitory computer-readable medium, user equipment, electronic device, wireless communication device, and/or processing system as substantially described with reference to, and as illustrated by, the specification and accompanying drawings. The foregoing paragraphs of this section have broadly summarized some aspects of the present disclosure. These and additional aspects and associated advantages will be described hereinafter. The disclosed aspects may be used as a basis for modifying or designing other aspects for carrying out the same or similar purposes of the present disclosure. Such equivalent aspects do not depart from the scope of the appended claims. Characteristics of the aspects disclosed herein, both their organization and method of operation, together with associated advantages, will be better understood from the following description when considered in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The appended drawings illustrate some aspects of the present disclo