US-12619274-B2 - Semiconductor device performing clock gating and operating method thereof

Abstract

A semiconductor device includes an intellectual property (IP) block configured to operate based on a first clock signal and a power voltage, a clock gating circuit configured to operate based on the power voltage, and generate the first clock signal by selectively performing clock gating on a second clock signal based on an enable signal, and a critical path monitor (CPM) configured to generate a digital code having a value, which varies according to a voltage drop of the power voltage, and activate the enable signal based on a comparison of the value of the digital code with a reference value.

Inventors

• Jaeyoung Lee
• Byungsu KIM
• Youngsan KIM
• Jaegon Lee
• Jaehoon Kim
• Byeongho LEE
• Jongjin Lee
• Wookyeong Jeong

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20240319

Priority Date

20230324

Claims (20)

1. 1 . A semiconductor device comprising: an intellectual property (IP) block configured to operate based on a first clock signal and a power voltage; a clock gating circuit configured to generate the first clock signal by selectively performing clock gating on a second clock signal based on an enable signal; and a critical path monitor (CPM) configured to operate based on the power voltage and generate a digital code having a value, which varies according to a voltage drop of the power voltage, and to activate the enable signal based on a comparison of the value of the digital code with a reference value.
2. 2 . The semiconductor device of claim 1 , wherein a value of the digital code decreases as the voltage drop increases.
3. 3 . The semiconductor device of claim 1 , wherein the CPM comprises: a waveform generator configured to generate a periodic waveform having a frequency that is less than a frequency of the first clock signal, and to generate and output a first sample waveform and a second sample waveform having an inverted level of the first sample waveform by sampling the periodic waveform at first edges of the first clock signal; a first waveform generation circuit configured to generate a first waveform by delaying the first sample waveform; a second waveform generation circuit configured to generate a second waveform by delaying the second sample waveform; and a comparator configured to generate the enable signal based on the value of the digital code, in which the first waveform is merged with the second waveform, and the reference value.
4. 4 . The semiconductor device of claim 3 , wherein the first waveform generation circuit comprises: a first delay circuit configured to generate a first delay sample waveform by adjusting a delay of the first sample waveform; and a first edge detector configured to generate the first waveform based on a comparison result between the first delay sample waveform and the first sample waveform, wherein the second waveform generation circuit comprises: a second delay circuit configured to generate a second delay sample waveform by adjusting a delay of the second sample waveform; and a second edge detector configured to generate the second waveform based on a comparison result between the second delay sample waveform and the second sample waveform.
5. 5 . The semiconductor device of claim 4 , wherein the CPM further comprises a selection circuit configured to generate the digital code by selectively outputting the first waveform or the second waveform based on the second sample waveform.
6. 6 . The semiconductor device of claim 1 , wherein the CPM is configured to: deactivate the enable signal if a value of the digital code is equal to or less than a first reference value, and activate the enable signal if the value of the digital code is greater than a second reference value, wherein the second reference value is different from the first reference value.
7. 7 . The semiconductor device of claim 1 , wherein the CPM is configured to deactivate the enable signal during a reference time if the value of the digital code is equal to or less than a reference value.
8. 8 . The semiconductor device of claim 1 , wherein the CPM is configured to update the value of the digital code at each cycle of the second clock signal.
9. 9 . An operating method of a semiconductor device, the operating method comprising: generating a first sample waveform and a second sample waveform having an inverted phase with respect to the first sample waveform by sampling an input waveform based on a first clock signal; generating a first waveform based on a comparison result between the first sample waveform and a first delay waveform generated by delaying the first sample waveform using a first delay circuit operating based on a power voltage; generating a second waveform based on a comparison result between the second sample waveform and a second delay waveform generated by delaying the second sample waveform using a second delay circuit operating based on the power voltage; generating an enable signal by comparing a value of a digital code, in which the first waveform is merged with the second waveform, with a reference value; and performing a clock gating on the first clock signal based on the enable signal.
10. 10 . The operating method of claim 9 , wherein the value of the digital code decreases as a voltage drop of the power voltage increases.
11. 11 . The operating method of claim 9 , wherein the generating of the enable signal comprises, generating the digital code by selectively outputting the first waveform and the sample waveform based on the second sample waveform.
12. 12 . The operating method of claim 9 , wherein the generating of the enable signal comprises: deactivating the enable signal in response to the value of the digital code being equal to or less than a first reference value; and activating the enable signal in response to the value of the digital code being greater than a second reference value, wherein the second reference value is different from the first reference value.
13. 13 . The operating method of claim 9 , wherein the generating of the enable signal comprises deactivating the enable signal during a reference time when the value of the digital code is equal to or less than the reference value.
14. 14 . The operating method of claim 9 , wherein the generating of the enable signal comprises updating the value of the digital code at each cycle of the first clock signal.
15. 15 . The operating method of claim 9 , wherein a cycle of the input waveform is at least twice a cycle of the first clock signal.
16. 16 . A semiconductor device comprising: a processor; a clock generator configured to generate a first clock signal; a clock gating circuit configured to generate a second clock signal provided to the processor by performing a clock gating on the first clock signal based on an enable signal; and a critical path monitor (CPM) configured to operate based on a power voltage, and adjust a deactivation time of the enable signal based on a magnitude of the power voltage, wherein the processor is configured to operated based on the first clock signal and the power voltage.
17. 17 . The semiconductor device of claim 16 , wherein the CPM increases the deactivation time of the enable signal as the power voltage decreases.
18. 18 . The semiconductor device of claim 16 , wherein the CPM generates a digital code representing a circuit delay due to a voltage drop of the power voltage, and deactivates the enable signal by comparing a value of the digital code with a reference value.
19. 19 . The semiconductor device of claim 18 , wherein the value of the digital code decreases as the power voltage decreases.
20. 20 . The semiconductor device of claim 18 , wherein the CPM comprises: a calibration delay circuit configured to adjust a delay of a sample waveform; a waveform generator configured to output a first sample waveform and a second sample waveform having an inverted level of the first sample waveform based on the first clock signal; a first waveform generation circuit configured to generate a first waveform by delaying the first sample waveform; a second waveform generation circuit configured to generate a second waveform by delaying the second sample waveform; and a comparator configured to generate the enable signal based on the value of the digital code, in which the first waveform is merged with the second waveform, and the reference value.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0039214, filed on Mar. 24, 2023 in the Korean Intellectual Property office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD This disclosure relates generally to semiconductor devices and more particularly to a semiconductor device performing clock gating to compensate for a voltage drop, and an operating method of the semiconductor device. DISCUSSION OF RELATED ART As the integration degree and complexity of semiconductor devices increase and the operating speed increases, the issue of low power consumption becomes a paramount factor. When power consumption is high, the temperature of a chip may increase, which causes the chip to operate slowly or even become inoperable. Moreover, the package may be damaged or its lifetime reduced. In semiconductor circuits within the semiconductor devices, circuits which provide or block clocks for power reduction are sometimes incorporated. A clock gating circuit may function to suspend clocks to a particular circuit and thereby control an overall frequency of an operation of the particular circuit. SUMMARY Embodiments of the inventive concept provide a semiconductor device, which monitors the operation speed of a circuit generated by a voltage drop at a fast response time and compensates for the voltage drop by performing clock gating for a clock signal, and an operating method of the semiconductor device. According to an aspect of the inventive concept, there is provided a semiconductor device including an intellectual property (IP) block configured to operate based on a first clock signal and a power voltage, a clock gating circuit configured to generate the first clock signal by selectively performing clock gating on a second clock signal based on an enable signal, and a critical path monitor (CPM) configured to operate based on the power voltage, generate a digital code having a value, which varies according to a voltage drop of the power voltage, and to activate the enable signal based on a comparison of the value of the digital code with a reference value. According to another aspect of the inventive concept, there is provided an operating method of a semiconductor device including generating a first sample waveform and a second sample waveform having an inverted phase with respect to the first sample waveform by sampling an input waveform based on a first clock signal, generating a first waveform based on a comparison result between the first sample waveform and a first delay waveform generated by delaying the first sample waveform using a first delay circuit operating based on a power voltage, and the first sample waveform, generating a second waveform based on a comparison result between the second sample waveform and a second delay waveform generated by delaying the second sample waveform using a second delay circuit operating based on the power voltage, and the second sample waveform, generating an enable signal by comparing a value of a digital code, in which the first waveform and the second waveform are merged, with a reference value, and performing a clock gating on the first clock signal based on the enable signal. According to another aspect of the inventive concept, there is provided a semiconductor device including a processor, a clock generator configured to generate a first clock signal, a clock gating circuit configured to generate a second clock signal provided to the processor by performing clock gating on the first clock signal based on an enable signal, and a CPM configured to operate based on a power voltage, and adjust a deactivation time of the enable signal based on a magnitude of the power voltage. According to another aspect of the inventive concept, there is provided a semiconductor device including: a processor; a clock generator configured to generate a first clock signal; a clock gating circuit configured to generate a second clock signal provided to the processor by performing a clock gating on the first clock signal based on an enable signal; and a CPM configured to monitor a critical path of the processor based on a power voltage, and to initiate a deactivation period of the enable signal using a binary code generated based on a magnitude of the power voltage. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a block diagram of a semiconductor device according to an embodiment; FIG. 2 is a diagram of a semiconductor system according to an embodiment; FIG. 3 is a circuit diagram of a power delivery network according to an embodiment; FIG. 4 is a block diagram of a critical path monitor (CPM) and a clock gating circuit according to an embodiment; FIG. 5 is a flowchart of an operating method of a semicondu