US-12619275-B2 - Access to multiple timing domains

Abstract

Examples described herein relate to a system-on-a-chip (SoC) comprising: a multiplexer integrated into the SoC, wherein the multiplexer comprises one or more physical layer (PHY) circuitries and the multiplexer is to receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes. In some examples, the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, network-attached appliance, and/or storage device.

Inventors

• Srinivasan S. Iyengar
• Paul KAPPLER
• Alon Meir
• Joseph MIRSKY
• Thomas Ng

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20211022

Claims (20)

1. 1 . An apparatus comprising: a system-on-a-chip (SoC) comprising: a multiplexer integrated into the SoC, wherein the multiplexer comprises one or more physical layer (PHY) circuitries and the multiplexer is to receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes, wherein: based on application of a first clock transfer configuration of the multiple clock distribution schemes by the multiplexer, at least one of the one or more PHY circuitries is to forward the received one or more clock signals to a different of the one or more PHY circuitries and at least one of the one or more PHY circuitries is to not forward the received one or more clock signals to another PHY circuitry, based on application of a second clock transfer configuration of the multiple clock distribution schemes by the multiplexer, the one or more PHY circuitries are not to forward the received one or more clock signals to another PHY circuitry, and based on application of a third clock transfer configuration of the multiple clock distribution schemes by the multiplexer, at least one of the one or more PHY circuitries is to forward the received one or more clock signals to a different of the one or more PHY circuitries.
2. 2 . The apparatus of claim 1 , wherein the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, network-attached appliance, and/or storage device.
3. 3 . The apparatus of claim 1 , wherein for the first clock transfer configuration, the multiplexer integrated into the SoC is to distribute a first clock signal to a plurality of PHY circuitries and a second clock signal to a second plurality of PHY circuitries.
4. 4 . The apparatus of claim 1 , wherein for the second clock transfer configuration, the multiplexer integrated into the SoC is to distribute: a first clock signal to a first PHY circuitry; a second clock signal to a second PHY circuitry; a third clock signal to a third PHY circuitry; and a fourth clock signal to a fourth PHY circuitry.
5. 5 . The apparatus of claim 1 , wherein for the second clock transfer configuration, the multiplexer integrated into the SoC is to distribute: a first clock signal to a first PHY circuitry and a second PHY circuitry and a third clock signal to a third PHY circuitry and a fourth PHY circuitry.
6. 6 . The apparatus of claim 1 , wherein for the third clock transfer configuration, the multiplexer integrated into the SoC is to distribute: a first clock signal to a first PHY circuitry and a second PHY circuitry; a second clock signal to a third PHY circuitry; and a third clock signal to a fourth PHY circuitry.
7. 7 . The apparatus of claim 1 , wherein the multiplexer integrated into the SoC comprises an integrated circuit that includes a network interface device, the multiplexer, and a device interface.
8. 8 . The apparatus of claim 1 , wherein the one or more PHY circuitries comprise a multiplexer and circuitry to (a) receive an input clock signal from a host system or a clock signal transferred from another PHY circuitry and (b) output a clock signal based on the input clock signal or the clock signal transferred from another PHY circuitry.
9. 9 . The apparatus of claim 1 , wherein the multiplexer is to support: common clocking with single host central processing unit (CPU), common but independent clocking with multiple host CPUs, and clocking for hybrid storage.
10. 10 . The apparatus of claim 1 , comprising at least one host server, wherein the at least one host server is conductively coupled to the SoC using a circuit board and wherein the at least one host server is to configure the SoC with the clock transfer configuration.
11. 11 . The apparatus of claim 10 , wherein the multiplexer integrated into the SoC comprises an integrated circuit that includes a network interface device, the multiplexer, and a device interface and comprising a data center comprising the at least one host server, wherein the data center comprises a receiver host system to receive packets from the network interface device.
12. 12 . A method comprising: in a system-on-a-chip (SoC) comprising a network interface device and a multiplexer integrated into the SoC: receiving one or more clock signals and distributing the one or more clock signals to one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes, wherein: based on utilization of a first clock transfer scheme of the multiple clock distribution schemes by the multiplexer, at least one of the one or more PHY circuitries forwarding the received one or more clock signals to a different of the one or more PHY circuitries and at least one of the one or more PHY circuitries not forwarding the received one or more clock signals to another PHY circuitry, based on utilization of a second clock transfer scheme of the multiple clock distribution schemes by the multiplexer, the one or more PHY circuitries not forwarding the received one or more clock signals to another PHY circuitry, and based on utilization of a third clock transfer scheme of the multiple clock distribution schemes by the multiplexer, at least one of the one or more PHY circuitries forwarding the received one or more clock signals to a different of the one or more PHY circuitries.
13. 13 . The method of claim 12 , wherein for the second clock transfer scheme, the multiplexer integrated into the SoC distributes a first clock signal to a set of two PHY circuitries and a second clock signal to a second set of two PHY circuitries.
14. 14 . The method of claim 12 , wherein for the second clock transfer scheme, the multiplexer performs distributing: a first clock signal to a first PHY circuitry; a second clock signal to a second PHY circuitry; a third clock signal to a third PHY circuitry; and a fourth clock signal to a fourth PHY circuitry.
15. 15 . The method of claim 12 , wherein for the second clock transfer scheme, the multiplexer performs distributing: a first clock signal to a first PHY circuitry and a second PHY circuitry and a third clock signal to a third PHY circuitry and a fourth PHY circuitry.
16. 16 . The method of claim 12 , wherein the SoC comprises an integrated circuit that includes a network interface device, the multiplexer, and a device interface.
17. 17 . The method of claim 12 , wherein the one or more PHY circuitries comprise a multiplexer and circuitry to (a) receive an input clock signal from a host system or a clock signal transferred from another PHY circuitry and (b) output a clock signal based on the input clock signal or the clock signal transferred from another PHY circuitry.
18. 18 . At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: configure a multiplexer comprising one or more physical layer (PHY) circuitries and integrated into a system-on-a-chip (SoC) comprising a network interface device to: receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes, wherein: utilization of a first clock transfer configuration by the multiplexer comprises at least one of the one or more PHY circuitries to forward the received one or more clock signals to a different of the one or more PHY circuitries and at least one of the one or more PHY circuitries not forwarding the received one or more clock signals to another PHY circuitry, utilization of a second clock transfer configuration by the multiplexer comprises the one or more PHY circuitries not forwarding the received one or more clock signals to another PHY circuitry, and utilization of a third clock transfer configuration by the multiplexer comprises at least one of the one or more PHY circuitries to forward the received one or more clock signals to a different of the one or more PHY circuitries.
19. 19 . The computer-readable medium of claim 18 , wherein the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, and/or storage device.
20. 20 . The computer-readable medium of claim 18 , wherein for the second clock transfer configuration, the multiplexer integrated into the SoC is to distribute a first clock signal to a set of two PHY circuitries and a second clock signal to a second set of two PHY circuitries.

Description

BACKGROUND Data centers provide computing resources for Internet-connected devices. Computing systems in a data center can utilize device-to-device connections for communications among devices. Various protocols and standards specify manners of device-to-device connections. Open Compute Project (OCP) is an organization involved in designing device-to-device connections for servers, data storage, racks, and switches. FIG. 1 illustrates a multi-host networking system based on Open Compute Project (OCP) NIC 3.0 version 1.1.0 (2021), where the various Peripheral Component Interconnect Express (PCIe) configurations (e.g., x16 (16 PCIe lanes per connector), x8 (8 PCIe lanes per connector), x4 (4 PCIe lanes per connector), and so forth) for host connectivity utilize a multiplexer connected to a platform circuit board and the multiplexer receives PCIe analog reference clock inputs from one or more host systems. For the circuit board to support configurations of 2 x8 or 4 x4 clock signals, a platform level clock multiplexer is implemented. For example, some platforms utilize a platform level clock multiplexer to support 2 x8 clock or 4 x4 clocks on the same reference board design. In addition, the platform or its microcontroller switches between various platform configurations to support configurations of x16, x8, or x4. Table of FIG. 2 outlines systems, based on OCP NIC 3.0 version 1.1.0, with multiple hosts connected to a network interface card (NIC) that support PCIe connectivity to more than one host via physical layer interfaces (PHY[0] to PHY[1]) of the NIC. The table of FIG. 2 shows different platform configurations that support multi-host, accelerator, storage (including hybrid storage (e.g., a mixture of random access memory, solid state drives (SSDs), and hard drive disks (HDD)), and hybrid systems. In some known implementations, supporting these different modes involves circuit board level changes, such as changes to jumpers or wires or unique reference boards. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a multi-host networking system. FIG. 2 shows different reference clock platform configurations. FIG. 3 depicts an example system. FIG. 4A depicts an example configuration that provides for receipt of multiple independent clock signals from multiple hosts. FIG. 4B depicts an example configuration that provides for receipt of multiple independent clock signals from multiple hosts. FIG. 4C depicts an example configuration that provides for receipt of multiple independent clock signals from multiple hosts. FIG. 4D depicts an example configuration that provides for distribution of a clock signal to multiple PHYs. FIG. 4E depicts an example of a network interface device. FIG. 5 depicts an example multiplexer system. FIGS. 6A-6C depict an example configuration. FIG. 7 depicts an example process. FIG. 8 depicts an example system. DETAILED DESCRIPTION Some examples provide a multiplexer integrated into a system on chip (SoC) or semiconductor die of a device and the multiplexer supports clock receipt from a single host central processing unit (CPU) as well as independent clock receipt from multiple host CPUs. The integrated multiplexer can support common clocking from a single host and common but independent clocking from multiple hosts for a device interface. The multiplexer, device interface, and device can be integrated in the same SoC. The integrated multiplexer can transfer one or more clock signals from one or more host systems and support configurations set forth, at least, in OCP NIC 3.0 version 1.1.0 (as well as earlier versions, later versions, and derivatives thereof). A platform with one set of circuit board signal routing can support multiple clock routing configurations with a single set of clock routing from one or more host devices to physical layer interfaces (PHYs) of the device interface. Some examples can utilize the integrated multiplexer to provide clock signals to the device interface that can change between different clock routing options. A circuit board that provides connectivity between one or more CPUs and the device SoC need not be changed to support different clock routing options, but in some examples, the circuit board may be modified to support different clock routing options. FIG. 3 depicts an example system. Platform circuit board 300 can include a printed circuit board (PCB), motherboard, or other circuit board with conductive connectors that provide communication via electrical and/or optical signals among host CPU0 302-0 to host CPU N−1 302-N−1 and network interface device 310. One or more of host CPU0 302-0 to host CPU N−1 302-N−1 can include one or more processor, central processing unit (CPU), core, graphics processing unit (GPU), general purpose GPU (GPGPU), accelerator, field programmable gate array (FPGA), application specific integrated circuit (ASIC), programmable hardware devices, memory, and interconnection devices. Note that one or more of host CPU0 302-0 to