US-12619276-B2 - Computer architecture having selectable parallel and serial communication channels between processors and memory

Abstract

A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Inventors

• Hao Wang
• Nam Sung Kim

Assignees

• WISCONSIN ALUMNI RESEARCH FOUNDATION

Dates

Publication Date

20260505

Application Date

20240813

Claims (18)

1. 1 . An electronic computer comprising: a processor system having: (a) a first processor; (b) a second processor; an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system at memory addresses, the electronic memory including a first memory bank having a first address range and a second memory bank having a second address range different from the first address range; a parallel bus communicating between the processor system and the first memory bank providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane and not communicating with the second memory bank; a serial bus communicating between the processor system and the second memory bank providing transmission of different bits of given data words serially on at least one conductor of a serial lane, and not communicating with the first memory bank; and a memory access manager: (a) providing communication between the electronic memory and the first processor on both of the parallel bus and the serial bus; (b) providing communication between the electronic memory and the second processor on both of the parallel bus and the serial bus; (c) dynamically selecting between the parallel bus and serial bus for communication between the electronic memory and each processor of the processor system as determined by a memory address of data being communicated falling within either of the first address range or second address range, wherein the serial bus provides multiple lanes each providing a bit rate of memory access words through a corresponding of the at least one conductor of at least 10 Gb per second; and wherein each lane transmits bits according to an independent clock for the lane provided by an embedded clock protocol within the transmitted data of the lane.
2. 2 . The electronic computer of claim 1 wherein the memory access manager identifies one of the parallel bus and serial bus for access of a given data word according to one of the processors first storing the given data word in the electronic memory.
3. 3 . The electronic computer of claim 1 wherein the electronic memory includes different memory banks exclusively accessible by one of the serial bus and parallel bus.
4. 4 . The electronic computer of claim 1 wherein the electronic memory allows access to data words according to address words and wherein the parallel bus provides transmission of multiple bits of each address word in parallel on separate conductors and the serial bus provides transmission of multiple bits of each address word in series on at least one conductor.
5. 5 . The electronic computer of claim 1 wherein the serial bus provides for multiple serial lanes and wherein the parallel bus has a single clock for synchronizing the parallel transmission of different bits on the separate conductors.
6. 6 . The electronic computer of claim 5 wherein the parallel bus employs a clock signal independent of digital words transmitted.
7. 7 . The electronic computer of claim 6 wherein the serial bus employs packet transmission in which multiple bits of words are transmitted in series as packets having header data and error correction data.
8. 8 . The electronic computer of claim 7 wherein the serial bus employs a low-voltage differential transmission on a conductor pair and wherein the parallel bus employs single-ended transmissions on a single conductor.
9. 9 . The electronic computer of claim 8 wherein the serial bus provides a bit rate on each conductor of at least 15 Gb per second.
10. 10 . The electronic computer of claim 1 wherein the serial bus has higher latency in communicating data words between the processor system and memory than the parallel bus.
11. 11 . The electronic computer of claim 1 wherein the first and second processor may both communicate with memory over either the serial bus or parallel bus.
12. 12 . The electronic computer of claim 1 wherein the memory access manager is implemented in part by software executed on the processor system.
13. 13 . The electronic computer of claim 1 wherein at least one of the first and second processors are general processing units.
14. 14 . The electronic computer of claim 1 wherein at least one of the first and second processors has at least 100 cores.
15. 15 . The electronic computer of claim 1 wherein at least one of first and second processors is a specialized processor for streaming data selected from the group of video data and audio data.
16. 16 . The electronic computer of claim 1 wherein at least one of the first and second processors and at least a portion of the parallel bus and serial bus are integrated circuits integrated on a common substrate.
17. 17 . The electronic computer of claim 1 wherein the electronic memory is dynamic random-access memory.
18. 18 . An electronic computer comprising: a processor system having: (a) a first processor; (b) a second processor; an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system at memory addresses, the electronic memory including a first memory bank having a first address range and a second memory bank having a second address range different from the first address range wherein the electronic memory is dynamic random-access memory; a parallel bus communicating between the processor system and the first memory bank providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane and not communicating with the second memory bank; a serial bus communicating between the processor system and the second memory bank providing transmission of different bits of given data words serially on at least one conductor of a serial lane, and not communicating with the first memory bank; and a memory access manager: (a) providing communication between the electronic memory and the first processor on both of the parallel bus and the serial bus; (b) providing communication between the electronic memory and the second processor on both of the parallel bus and the serial bus; (c) dynamically selecting between the parallel bus and serial bus for communication between the electronic memory and each processor of the processor system as determined by a memory address of data being communicated falling within either of the first address range or second address range.

Description

CROSS REFERENCE TO RELATED APPLICATION This patent application is a continuation of U.S. patent application Ser. No. 18/230,418 filed Aug. 4, 2023, which is a continuation of U.S. patent application Ser. No. 16/135,778 filed Sep. 19, 2018, which is a divisional patent application of U.S. patent application Ser. No. 14/267,190 filed May 1, 2014, all incorporated by reference. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with government support under 1217102 awarded by the National Science Foundation. The government has certain rights in the invention. BACKGROUND OF THE INVENTION The present invention relates to computer architectures and in particular to a computer and memory system providing both parallel and serial buses for communicating between processors and memory. Modern computer processors can process data faster than the data can be exchanged with external memory. For this reason, there is considerable interest in increasing the “bandwidth” of the memory bus communicating between processors and external memory so that faster data transfers can occur and processor speed may be better utilized. The bandwidth of a memory bus is a function both of the transmission speed of the memory bus (the number of bits that can be transmitted per second) and the width of the memory bus (the number of bits that can be transmitted simultaneously). Typical memory buses are parallel buses employing multiple conductors that simultaneously transmit multiple bits of data words at a high bit rate. A data word is the unit of data (number of bits) that the processor can simultaneously process. Increasing the bandwidth of a memory bus can be obtained by increasing transmission speed or memory bus width. Increasing the memory bus width, or number of parallel conductors in the memory bus, is practically limited by constraints in the number of pins (terminals) that can be physically added to processor and memory integrated circuit packages. Currently over 130 I/O pins are required for DDR3 (double data rate type III synchronous dynamic random access memory). Increasing the speed of each parallel conductor is limited by degradation of the transmitted data resulting from increased crosstalk between parallel data lines and attenuation of the signal at high speeds. To some extent, these signal degradation problems can be addressed by increasing transmission power but at the cost of greatly increasing power usage that rises disproportionately (super linearly) to speed increases. Increasing the speed of the memory bus also causes a skewing or phase shifting of the data transmitted on separate parallel conductors with respect to the common clock, introducing errors in reconstructing the data at the end of the bus. SUMMARY OF THE INVENTION The present invention substantially increases memory bus bandwidth by combining a parallel memory bus with a high-speed serial memory bus. A serial memory bus normally introduces too much latency (delay between a read request and receiving the data) for general computer processors, but the present inventors have recognized that this latency can be accommodated by important special computer processors such as graphic processing units (GPU's) and streaming processors used for decoding video and audio. By selectively steering some memory traffic between the special computer processors and memory to a high latency, serial memory bus, the total memory bandwidth may be substantially increased while still providing low latency when needed by means of the parallel memory bus. Specifically, in one embodiment, the invention provides an electronic computer having a processor system including at least a first latency-sensitive processor and a second latency-insensitive processor. The latency-sensitive processor executes a general instruction set for general purpose computation while the latency-insensitive processor executes a specialized instruction set and is less sensitive to latency in access to electronic memory than the latency-sensitive processor. An electronic memory communicates with the processor system and stores data words for reading and writing by the processor system. A parallel bus communicates between the processor system and the memory providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane, and a serial bus communicates between the processor system and the memory providing transmission of different bits of given data words serially on at least one conductor of a serial lane. A memory access manager controls the memory accesses to preferentially route memory access by the latency-sensitive processor through the parallel bus and memory access by the latency-insensitive processor through the serial bus. It is thus a feature of at least one embodiment of the invention to increase the effective bandwidth of a low-latency parallel memory bus by channeling some latency tolerant data through a high-spe