US-12619293-B2 - Power management message aggregation

US12619293B2US 12619293 B2US12619293 B2US 12619293B2US-12619293-B2

Abstract

Aspects relate to mechanisms for an apparatus to aggregate latency tolerance reporting (LTR) messages from a plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency across the plurality of endpoints. The minimum snoop latency and minimum no-snoop latency are provided to a processor configured for power management of the apparatus.

Inventors

Ramacharan Sundararaman
Ravikiran KAIDALA LAKSHMAN
Shrinivas Venkatraman

Assignees

QUALCOMM INCORPORATED

Dates

Publication Date: 20260505
Application Date: 20240327

Claims (20)

1 . An apparatus, comprising: a root complex comprising a controller coupled to a processor via an upstream connection and to a plurality of endpoints via respective downstream connections; and an aggregator circuit within the controller, the aggregator circuit configured to: receive respective latency tolerance reporting (LTR) messages from one or more of the plurality of endpoints; aggregate the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency; store respective latest snoop latencies and respective latest no-snoop latencies for each of a plurality root ports coupled to the plurality of endpoints in a register, wherein the respective latest snoop latencies comprise the minimum snoop latency and the respective latest no-snoop latencies comprise the minimum no-snoop latency; determine a link-down event occurred for a link associated with a root port of the plurality of root ports, the root port having at least one of the minimum snoop latency or the minimum no-snoop latency associated therewith; update at least one of the minimum snoop latency to a next minimum snoop latency from the respective latest snoop latencies or the minimum no-snoop latency to a next minimum no-snoop latency from the respective latest no-snoop latencies based on the link-down event; and transmit the minimum snoop latency and the minimum no-snoop latency to the processor configured for power management.
2 . The apparatus of claim 1 , wherein the aggregator circuit is further configured to: identify a new snoop latency from the respective LTR messages; compare the new snoop latency to a previously stored minimum snoop latency; and update the minimum snoop latency in response to the new snoop latency being less than the previously stored minimum snoop latency.
3 . The apparatus of claim 2 , wherein the aggregator circuit is further configured to: identify a new no-snoop latency from the respective LTR messages; compare the new no-snoop latency to a previously stored minimum no-snoop latency; and update the minimum no-snoop latency in response to the new no-snoop latency being less than the previously stored minimum no-snoop latency.
4 . The apparatus of claim 1 , wherein the minimum snoop latency comprises a conglomerated snoop latency and the minimum no-snoop latency comprises a conglomerated no-snoop latency, wherein the conglomerated snoop latency and the conglomerated no-snoop latency each account for at least one of downstream latency to the plurality of endpoints or upstream latency to the processor.
5 . The method of claim 1 , further comprising: identifying a reset event; and transmitting a maximum snoop latency and a maximum no-snoop latency in response to the reset event.
6 . The method of claim 1 , wherein the minimum snoop latency and the minimum no-snoop latency control power management actions of the processor.
7 . A method of power management message aggregation, the method comprising: receiving, at a controller of a root complex, respective latency tolerance reporting (LTR) messages from one or more of a plurality of endpoints coupled to the controller via respective downstream connections; aggregating the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency; storing respective latest snoop latencies and respective latest no-snoop latencies for each of a plurality root ports coupled to the plurality of endpoints in a register, wherein the respective latest snoop latencies comprise the minimum snoop latency and the respective latest no-snoop latencies comprise the minimum no-snoop latency; determining a link-down event occurred for a link associated with a root port of the plurality of root ports, the root port having at least one of the minimum snoop latency or the minimum no-snoop latency associated therewith; updating at least one of the minimum snoop latency to a next minimum snoop latency from the respective latest snoop latencies or the minimum no-snoop latency to a next minimum no-snoop latency from the respective latest no-snoop latencies based on the link-down event; and transmitting the minimum snoop latency and the minimum no-snoop latency to a processor configured for power management, wherein the processor is coupled to the controller via an upstream connection.
8 . The method of claim 7 , further comprising: identifying a new snoop latency from the respective LTR messages; comparing the new snoop latency to a previously stored minimum snoop latency; and updating the minimum snoop latency in response to the new snoop latency being less than the previously stored minimum snoop latency.
9 . The method of claim 8 , further comprising: identifying a new no-snoop latency from the respective LTR messages; comparing the new no-snoop latency to a previously stored minimum no-snoop latency; and updating the minimum no-snoop latency in response to the new no-snoop latency being less than the previously stored minimum no-snoop latency.
10 . The method of claim 7 , wherein the minimum snoop latency comprises a conglomerated snoop latency and the minimum no-snoop latency comprises a conglomerated no-snoop latency, wherein the conglomerated snoop latency and the conglomerated no-snoop latency each account for at least one of downstream latency to the plurality of endpoints or upstream latency to the processor.
11 . The method of claim 7 , further comprising: identifying a reset event; and transmitting a maximum snoop latency and a maximum no-snoop latency in response to the reset event.
12 . The method of claim 7 , wherein the minimum snoop latency and the minimum no-snoop latency control power management actions of the processor.
13 . An apparatus at a root complex, comprising: means for receiving respective latency tolerance reporting (LTR) messages from one or more of a plurality of endpoints coupled to the root complex via respective downstream connections; means for aggregating the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency; means for storing respective latest snoop latencies and respective latest no-snoop latencies for each of a plurality root ports coupled to the plurality of endpoints in a register, wherein the respective latest snoop latencies comprise the minimum snoop latency and the respective latest no-snoop latencies comprise the minimum no-snoop latency; means for determining a link-down event occurred for a link associated with a root port of the plurality of root ports, the root port having at least one of the minimum snoop latency or the minimum no-snoop latency associated therewith; means for updating at least one of the minimum snoop latency to a next minimum snoop latency from the respective latest snoop latencies or the minimum no-snoop latency to a next minimum no-snoop latency from the respective latest no-snoop latencies based on the link-down event; and means for transmitting the minimum snoop latency and the minimum no-snoop latency to a processor configured for power management via an upstream connection.
14 . The apparatus of claim 13 , further comprising: means for identifying a new snoop latency from the respective LTR messages; means for comparing the new snoop latency to a previously stored minimum snoop latency; and means for updating the minimum snoop latency in response to the new snoop latency being less than the previously stored minimum snoop latency.
15 . The apparatus of claim 14 , further comprising: means for identifying a new no-snoop latency from the respective LTR messages; means for comparing the new no-snoop latency to a previously stored minimum no-snoop latency; and means for updating the minimum no-snoop latency in response to the new no-snoop latency being less than the previously stored minimum no-snoop latency.
16 . The apparatus of claim 13 , wherein the minimum snoop latency comprises a conglomerated snoop latency and the minimum no-snoop latency comprises a conglomerated no-snoop latency, wherein the conglomerated snoop latency and the conglomerated no-snoop latency each account for at least one of downstream latency to the plurality of endpoints or upstream latency to the processor.
17 . The apparatus of claim 13 , further comprising: means for identifying a reset event; and means for transmitting a maximum snoop latency and a maximum no-snoop latency in response to the reset event.
18 . The apparatus of claim 13 , wherein the minimum snoop latency and the minimum no-snoop latency control power management actions of the processor.
19 . A computing device, comprising: a processor configured for power management; and a root complex comprising a controller coupled to a plurality of endpoints via respective downstream connections and to the processor via an upstream connection, the controller configured to: receive respective latency tolerance reporting (LTR) messages from one or more of the plurality of endpoints; aggregate the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency; store respective latest snoop latencies and respective latest no-snoop latencies for each of a plurality root ports coupled to the plurality of endpoints in a register, wherein the respective latest snoop latencies comprise the minimum snoop latency and the respective latest no-snoop latencies comprise the minimum no-snoop latency; determine a link-down event occurred for a link associated with a root port of the plurality of root ports, the root port having at least one of the minimum snoop latency or the minimum no-snoop latency associated therewith; update at least one of the minimum snoop latency to a next minimum snoop latency from the respective latest snoop latencies or the minimum no-snoop latency to a next minimum no-snoop latency from the respective latest no-snoop latencies based on the link-down event; and transmit the minimum snoop latency and the minimum no-snoop latency to the processor.
20 . The computing device of claim 19 , wherein the controller is further configured to: identify a new snoop latency from the respective LTR messages; compare the new snoop latency to a previously stored minimum snoop latency; and update the minimum snoop latency in response to the new snoop latency being less than the previously stored minimum snoop latency.

Description

TECHNICAL FIELD The technology discussed below relates generally to data communication interfaces, and more particularly, to power management based on latency requirements of devices coupled via data communication interfaces. INTRODUCTION High-speed data communication interfaces are frequently used between circuits and components of mobile wireless devices and other complex systems. For example, certain devices may include processing, communications, storage, and/or display devices that interact with one another through one or more high-speed interfaces. Some of these devices, including synchronous dynamic random-access memory (SDRAM), may be capable of providing or consuming data and control information at processor clock rates. Other devices, e.g., display controllers, may use variable amounts of data at relatively low video refresh rates. The peripheral component interconnect express (PCIe) standard is an example of a high-speed data communication interface that supports a high-speed link capable of transmitting data at multiple gigabits per second. PCIe provides lower latency and higher data transfer rates compared to parallel buses. PCIe is specified for communication between a wide range of different devices. Typically, one device, e.g., a processor or hub, acts as a host, that communicates with multiple devices, referred to as endpoints, through PCIe links. The peripheral devices or components may include graphics adapter cards, network interface cards (NICs), storage accelerator devices, mass storage devices, Input/Output interfaces, and other high-performance peripherals. BRIEF SUMMARY OF SOME EXAMPLES The following presents a summary of one or more aspects of the present disclosure, in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a form as a prelude to the more detailed description that is presented later. In one example, an apparatus is provided. The apparatus includes a controller coupled to a plurality of endpoints and an aggregator circuit within the controller. The aggregator circuit is configured to receive respective latency tolerance reporting (LTR) messages from one or more of the plurality of endpoints, aggregate the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency, and transmit the minimum snoop latency and the minimum no-snoop latency to a processor configured for power management. Another example provides a method of power management message aggregation. The method includes receiving respective latency tolerance reporting (LTR) messages from one or more of a plurality of endpoints, aggregating the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency, and transmitting the minimum snoop latency and the minimum no-snoop latency to a processor configured for power management. Another example provides an apparatus. The apparatus includes means for receiving respective latency tolerance reporting (LTR) messages from one or more of a plurality of endpoints, means for aggregating the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency, and means for transmitting the minimum snoop latency and the minimum no-snoop latency to a processor configured for power management. Another example provides a computing device. The computing device includes a processor configured for power management and a controller coupled to a plurality of endpoints. The controller is configured to receive respective latency tolerance reporting (LTR) messages from one or more of the plurality of endpoints, aggregate the respective LTR messages across the plurality of endpoints to identify a minimum snoop latency and a minimum no-snoop latency, and transmit the minimum snoop latency and the minimum no-snoop latency to a processor configured for power management. These and other aspects will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and examples will become apparent to those of ordinary skill in the art upon reviewing the following description of specific exemplary aspects in conjunction with the accompanying figures. While features may be discussed relative to certain examples and figures below, all examples can include one or more of the features discussed herein. In other words, while one or more examples may be discussed as having certain features, one or more of such features may also be used in accordance with the various examples discussed herein. Similarly, while examples may be discuss