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US-12619356-B2 - Fragmentation management for memory systems

US12619356B2US 12619356 B2US12619356 B2US 12619356B2US-12619356-B2

Abstract

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide media fragmentation management. The controller receives, from a host, a file-based-optimization (FBO) entry comprising a plurality of logical block addresses (LBAs) associated with a file. The controller accesses a page table that associates the plurality of LBAs with respective physical addresses of a set of memory components and determines a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs. The controller computes a regression level for the file based on the first quantity of read operations relative to a second quantity of LBAs included in the plurality of LBAs.

Inventors

  • Nitul Gohain
  • Nicola Colella

Assignees

  • MICRON TECHNOLOGY, INC.

Dates

Publication Date
20260505
Application Date
20231025
Priority Date
20221215

Claims (20)

  1. 1 . A system comprising: a set of memory components of a memory sub-system; and a processing device operatively coupled to the set of memory components, the processing device being programmed to perform operations comprising: receiving, from a host, a file-based-optimization (FBO) entry comprising a plurality of logical block addresses (LBAs) associated with a file; accessing a page table that associates the plurality of LBAs with respective physical addresses of the set of memory components; determining a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs; determining a second quantity of LBAs representing how many LBAs are included among the plurality of LBAs; and computing a regression level for the file based on the first quantity of read operations that need to be performed to read data relative to the second quantity of LBAs that represent how many LBAs are included among the plurality of LBAs, the regression level computed as a ratio of the first quantity of read operations to a maximum number of read operations that need to be performed to read data associated with the plurality of LBAs.
  2. 2 . The system of claim 1 , wherein the operations for determining the first quantity of read operations comprise: determining whether an adjacent pair of the plurality of LBAs stored in the page table is associated with non-adjacent respective physical addresses, the first quantity of read operations being computed based on determining that the adjacent pair is associated with the non-adjacent respective physical addresses.
  3. 3 . The system of claim 1 , the operations comprising: identifying a plurality of adjacent pairs of the plurality of LBAs stored in the table that is each associated with respective sets of non-adjacent respective physical addresses; and computing the first quantity of read operations as a function of a quantity of the identified plurality of adjacent pairs.
  4. 4 . The system of claim 1 , the operations comprising: determining the maximum number of read operations that need to be performed to read the data associated with the plurality of LBAs, wherein the second quantity of LBAs corresponds to the maximum number of read operations.
  5. 5 . The system of claim 1 , the operations comprising: transmitting the regression level to the host in response to receiving the FBO entry.
  6. 6 . The system of claim 1 , the operations comprising: performing one or more data defragmentation operations based on comparing the regression level of the file to a threshold regression level comprising: identifying a first set of physical addresses associated with a first set of the plurality of LBAs that corresponds to a same channel of the set of memory components as a second set of physical addresses associated with a second set of the plurality of LBAs, the first set of physical addresses corresponding to a first chip enable and the second set of physical addresses corresponding to a second chip enable on the same channel; and instructing the same channel of the set of memory components to interleave reading the second set of physical addresses based on the second chip enable with transferring data read from the first set of physical addresses to the processing device.
  7. 7 . The system of claim 1 , the operations comprising: comparing the regression level of the file to a threshold regression level; and performing one or more data defragmentation operations based on comparing the regression level of the file to the threshold regression level.
  8. 8 . The system of claim 7 , wherein the one or more data defragmentation operations are performed in response to determining that the regression level of the file transgresses the threshold regression level.
  9. 9 . The system of claim 7 , wherein the one or more data defragmentation operations comprise modifying a read order for the physical addresses of the set of memory components associated with the plurality of LBAs.
  10. 10 . The system of claim 9 , wherein modifying the read order comprises: identifying a first set of physical addresses associated with a first set of the plurality of LBAs that corresponds to a same channel of the set of memory components as a second set of physical addresses associated with a second set of the plurality of LBAs, the first set of physical addresses corresponding to a first chip enable and the second set of physical addresses corresponding to a second chip enable on the same channel; and instructing the same channel of the set of memory components to interleave reading the second set of physical addresses based on the second chip enable with transferring data read from the first set of physical addresses to the processing device.
  11. 11 . The system of claim 10 , the operations comprising: instructing the same channel of the set of memory components to read the data from the first set of physical addresses based on the first chip enable; and after the data is read from the first set of physical addresses and while the data is transferred from the set of memory components to the processing device, instructing the same channel of the set of memory components to read data from the second set of physical addresses based on the second chip enable.
  12. 12 . The system of claim 10 , wherein a last LBA in the first set of the plurality of LBAs is non-adjacent to a first LBA in the second set of the plurality of LBAs.
  13. 13 . The system of claim 7 , the operations comprising: determining a type of storage associated with one or more of the physical addresses; transmitting, based on the comparing the regression level of the file to the threshold regression level, a first regression indicator to the host in response to determining that the type of storage associated with the one or more physical addresses is a first type; and transmitting, based on the comparing the regression level of the file to the threshold regression level, a second regression indicator to the host in response to determining that the type of storage associated with the one or more physical addresses is a second type.
  14. 14 . The system of claim 7 , wherein the one or more data defragmentation operations comprise copying data associated with non-adjacent physical addresses of the physical addresses associated with the plurality of LBAs to a new virtual block.
  15. 15 . The system of claim 14 , the operations comprising: determining that a quantity of free virtual blocks resulting from copying the data into the new virtual block is reduced below a threshold.
  16. 16 . The system of claim 14 , the operations comprising: determining that less than all of the new virtual block is populated by the copied data of the plurality of LBAs; and in response to determining that less than all of the new virtual block is populated by the copied data of the plurality of LBAs, placing other data associated with different LBAs into remaining portions of the new virtual block.
  17. 17 . A method comprising: receiving, from a host, a file-based-optimization (FBO) entry comprising a plurality of logical block addresses (LBAs) associated with a file; accessing a page table that associates the plurality of LBAs with respective physical addresses of a set of memory components; determining a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs; and determining a second quantity of LBAs representing how many LBAs are included among the plurality of LBAs; and computing a regression level for the file based on the first quantity of read operations that need to be performed to read data relative to the second quantity of LBAs that represent how many LBAs are included among the plurality of LBAs, the regression level computed as a ratio of the first quantity of read operations to a maximum number of read operations that need to be performed to read data associated with the plurality of LBAs.
  18. 18 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving, from a host, a file-based-optimization (FBO) entry comprising a plurality of logical block addresses (LBAs) associated with a file; accessing a page table that associates the plurality of LBAs with respective physical addresses of a set of memory components; determining a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs; and determining a second quantity of LBAs representing how many LBAs are included among the plurality of LBAs; and computing a regression level for the file based on the first quantity of read operations that need to be performed to read data relative to the second quantity of LBAs that represent how many LBAs are included among the plurality of LBAs, the regression level computed as a ratio of the first quantity of read operations to a maximum number of read operations that need to be performed to read data associated with the plurality of LBAs.
  19. 19 . A system comprising: a set of memory components of a memory sub-system; and a processing device operatively coupled to the set of memory components, the processing device being programmed to perform operations comprising: performing one or more data defragmentation operations based on comparing a regression level of a file to a threshold regression level; identifying a first set of physical addresses associated with a first set of a plurality of logical block addresses (LBAs) that corresponds to a same channel of the set of memory components as a second set of physical addresses associated with a second set of the plurality of LBAs, the first set of physical addresses corresponding to a first chip enable and the second set of physical addresses corresponding to a second chip enable on the same channel; and instructing the same channel of the set of memory components to interleave reading the second set of physical addresses based on the second chip enable with transferring data read from the first set of physical addresses to the processing device.
  20. 20 . A system comprising: a set of memory components of a memory sub-system; and a processing device operatively coupled to the set of memory components, the processing device being programmed to perform operations comprising: determining a type of storage associated with one or more of physical addresses; transmitting, based on comparing a regression level of a file to a threshold regression level, a first regression indicator to a host system in response to determining that the type of storage associated with the one or more physical addresses is a first type; and transmitting, based on the comparing the regression level of the file to the threshold regression level, a second regression indicator to the host system in response to determining that the type of storage associated with the one or more physical addresses is a second type.

Description

PRIORITY APPLICATION This application claims the benefit of priority to Indian Patent Application Serial Number 202241072538, filed Dec. 15, 2022, which is incorporated herein by reference in its entirety. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems and, more specifically, to providing adaptive media management for memory components, such as memory dies. BACKGROUND A memory sub-system can be a storage system, such as a solid-state drive (SSD), and can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. In general, a host system can utilize a memory sub-system to store data on the memory components and to retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 2 is a block diagram of an example media operations manager, in accordance with some implementations of the present disclosure. FIG. 3 is a block diagram of an example page table, in accordance with some implementations of the present disclosure. FIG. 4 is a block diagram of an example set of channels for multiple memory dies, in accordance with some implementations of the present disclosure. FIGS. 5A and 5B are flow diagrams of example methods to manage data fragmentation, in accordance with some implementations of the present disclosure. FIG. 6 is a block diagram illustrating a diagrammatic representation of a machine in the form of a computer system within which a set of instructions can be executed for causing the machine to perform any one or more of the methodologies discussed herein, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform different memory management operations (e.g., defragmentation operations) on different groups of memory components (e.g., memory dies) based on the respective regression levels (level of fragmentation) of files corresponding to data stored in the memory components. The memory sub-system controller can receive a file-based-optimization (FBO) entry from a host which identifies logical block addresses (LBAs) of one or more files. Using the FBO entry, the memory sub-system controller can determine a regression level of the file based on computing how many read operations need to be performed to retrieve the data from the memory components corresponding to the one or more files. The regression level can be communicated back to the host to determine whether there is a need to perform one or more defragmentation operations. For example, if the regression level transgresses a threshold regression level, the host can instruct the memory sub-system controller to de-fragment the data by copying as much of the data as possible into fewer memory blocks to reduce the number of read operations needed to be performed to read the LBAs of the one or more files. If the regression level does not transgress the threshold regression level, the memory sub-system controller may perform other types of defragmentation operations to improve the efficiency at which the data is read from the corresponding physical block addresses. By dynamically tailoring different media management operations (e.g., defragmentation operations) to the regression level of data corresponding to one or more files, the overall efficiency of operating the memory sub-system is improved. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more memory components, such as memory devices (e.g., memory dies) that store data. The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data at the memory sub-system and to read data from the memory sub-system. The data (or set of data) specified by the host is hereinafter referred to as “host data,” “application data,” or “user data”. The memory sub-system can initiate media management operations, such as a write operation, on host data that is stored on a memory device. For example, firmware of the memory sub-system may re-write previously written host data from a location on a memory device to a new location as part of garbage collection management operations. The data that is re-written, for example as initiated by the firmware, is hereinafter referred to as “garbage collection data”.