US-12619357-B2 - Memory system controlling nonvolatile memory

US12619357B2US 12619357 B2US12619357 B2US 12619357B2US-12619357-B2

Abstract

According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

Inventors

Naoki Esaka
Shinichi Kanno

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260505
Application Date: 20240801
Priority Date: 20200116

Claims (20)

1 . A method of controlling a nonvolatile memory, the nonvolatile memory including a plurality of first storage regions and a second storage region, each of the plurality of first storage regions and the second storage region including a memory cell, the method comprising: obtaining, from a write buffer of a host, first write data associated with one or more first write requests, the one or more first write requests being for writing data to a first write destination storage region allocated from the plurality of first storage regions; writing the first write data to the first write destination storage region in a first write mode for writing m-bit data per memory cell, m being an integer greater than or equal to two; obtaining, from the write buffer of the host, second write data associated with one or more second write requests, the one or more second write requests being for writing data to a second write destination storage region allocated from the plurality of first storage regions; writing the second write data to the second write destination storage region in the first write mode; and in causing a state of one of the plurality of first storage regions to transition from a first state of being allocated as a write destination storage region in which writing of data is possible to a second state in which writing of data is suspended, obtaining, from the write buffer of the host, third write data which are associated with the one or more first write requests and have not been obtained; writing the third write data to the second storage region shared by the plurality of first storage regions, in a second write mode for writing n-bit data per memory cell, n being an integer greater than or equal to one and less than or equal to m; and causing the state of the one of the plurality of first storage regions to transition from the first state to the second state.
2 . The method of claim 1 , wherein the nonvolatile memory includes a plurality of blocks each including a plurality of word lines each connecting a plurality of memory cells, the first write mode is a write mode in which data written in the memory cells of a first word line of the plurality of word lines of a block allocated to each first storage region do not become readable from the memory cells of the first word line by writing the data only to the memory cells of the first word line but become readable from the memory cells of the first word line after data are written to the memory cells of one or more word lines subsequent to the first word line, and the method further comprises: storing, in a buffer, the first write data obtained from the write buffer of the host before writing the first write data to the first write destination storage region; obtaining, from the buffer, the first write data which have not become readable from a block allocated to the first write destination storage region; and writing the third write data, together with the obtained first write data, to the second storage region in the second write mode.
3 . The method of claim 2 , wherein the second write mode is a write mode in which data written in the memory cells of a second word line of the plurality of word lines of each block become readable from the memory cells of the second word line by writing the data only to the memory cells of the second word line.
4 . The method of claim 1 , further comprising: in causing the state of the one of the plurality of first storage regions to transition from the first state to the second state while the second storage region is entirely filled with data written in the second write mode, selecting a third storage region from the plurality of first storage regions; and writing the third write data to the selected third storage region in the second write mode.
5 . The method of claim 1 , further comprising: receiving, from the host, a write request for writing data to the one of the plurality of first storage regions which has transitioned to the second state; and in response to receiving the write request, causing the state of the one of the plurality of first storage regions to transition from the second state to the first state.
6 . The method of claim 1 , further comprising: classifying write requests received from the host into a first group including the one or more first write requests for the first write destination storage region and a second group including the one or more second write requests for the second write destination storage region; determining that a first total size of write data associated with the one or more first write requests belonging to the first group has reached a first minimum write size of the first write destination storage region; in response to determining that the first total size has reached the first minimum write size, obtaining the first write data which has the first minimum write size, from the write buffer of the host; determining that a second total size of write data associated with the one or more second write requests belonging to the second group has reached a second minimum write size of the second write destination storage region; and in response to determining that the second total size has reached the second minimum write size, obtaining the second write data which has the second minimum write size, from the write buffer of the host.
7 . The method of claim 1 , further comprising: determining that the second storage region becomes defective; and in response to determining that the second storage region becomes defective, allocating another one of the plurality of first storage regions for writing the third write data in the second write mode.
8 . The method of claim 7 , wherein the writing of the third write data is performed on the second storage region unless the second storage region is defective.
9 . The method of claim 1 , wherein the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation, and each of the plurality of first storage regions is a group of two or more of the plurality of blocks.
10 . The method of claim 1 , wherein the transition of the state of the one of the plurality of first storage regions is performed based on a request from the host.
11 . A controller configured to control a nonvolatile memory, the nonvolatile memory including a plurality of first storage regions and a second storage region, each of the plurality of first storage regions and the second storage region including a memory cell, the controller comprising: an interface configured to be connected with a host; and a circuit configured to: obtain, from a write buffer of the host, first write data associated with one or more first write requests, the one or more first write requests being for writing data to a first write destination storage region allocated from the plurality of first storage regions; write the first write data to the first write destination storage region in a first write mode for writing m-bit data per memory cell, m being an integer greater than or equal to two; obtain, from the write buffer of the host, second write data associated with one or more second write requests, the one or more second write requests being for writing data to a second write destination storage region allocated from the plurality of first storage regions; write the second write data to the second write destination storage region in the first write mode; and in causing a state of one of the plurality of first storage regions to transition from a first state of being allocated as a write destination storage region in which writing of data is possible to a second state in which writing of data is suspended, obtain, from the write buffer of the host, third write data which are associated with the one or more first write requests and have not been obtained; write the third write data to the second storage region shared by the plurality of first storage regions, in a second write mode for writing n-bit data per memory cell, n being an integer greater than or equal to one and less than or equal to m; and cause the state of the one of the plurality of first storage regions to transition from the first state to the second state.
12 . The controller of claim 11 , wherein the nonvolatile memory includes a plurality of blocks each including a plurality of word lines each connecting a plurality of memory cells, the first write mode is a write mode in which data written in the memory cells of a first word line of the plurality of word lines of a block allocated to each first storage region do not become readable from the memory cells of the first word line by writing the data only to the memory cells of the first word line but become readable from the memory cells of the first word line after data are written to the memory cells of one or more word lines subsequent to the first word line, and the circuit is further configured to: store, in a buffer, the first write data obtained from the write buffer of the host before writing the first write data to the first write destination storage region; obtain, from the buffer, the first write data which have not become readable from a block allocated to the first write destination storage region; and write the third write data, together with the obtained first write data, to the second storage region in the second write mode.
13 . The controller of claim 12 , wherein the second write mode is a write mode in which data written in the memory cells of a second word line of the plurality of word lines of each block become readable from the memory cells of the second word line by writing the data only to the memory cells of the second word line.
14 . The controller of claim 11 , wherein the circuit is further configured to: in causing the state of the one of the plurality of first storage regions to transition from the first state to the second state while the second storage region is entirely filled with data written in the second write mode, select a third storage region from the plurality of first storage regions; and write the third write data to the selected third storage region in the second write mode.
15 . The controller of claim 11 , wherein the circuit is further configured to: receive, from the host, a write request for writing data to the one of the plurality of first storage regions which has transitioned to the second state; and in response to receiving the write request, cause the state of the one of the plurality of first storage regions to transition from the second state to the first state.
16 . The controller of claim 11 , wherein the circuit is further configured to: classify write requests received from the host into a first group including the one or more first write requests for the first write destination storage region and a second group including the one or more second write requests for the second write destination storage region; in response to determining that a first total size of write data associated with the one or more first write requests belonging to the first group has reached a first minimum write size of the first write destination storage region, obtain the first write data which has the first minimum write size, from the write buffer of the host; and in response to determining that a second total size of write data associated with the one or more second write requests belonging to the second group has reached a second minimum write size of the second write destination storage region, obtain the second write data which has the second minimum write size, from the write buffer of the host.
17 . The controller of claim 11 , wherein the circuit is further configured to: in response to determining that the second storage region becomes defective, allocate another one of the plurality of first storage regions for writing the third write data in the second write mode.
18 . The controller of claim 17 , wherein the writing of the third write data is performed on the second storage region unless the second storage region is defective.
19 . The controller of claim 11 , wherein the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation, and each of the plurality of first storage regions is a group of two or more of the plurality of blocks.
20 . The controller of claim 11 , wherein the transition of the state of the one of the plurality of first storage regions is performed based on a request from the host.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. Application Ser. No. 18/327,108 filed Jun. 1, 2023, which is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. Application Ser. No. 17/536,558 filed Nov. 29, 2021, which is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. Application Ser. No. 17/019,955 filed Sep. 14, 2020, which is based upon and claims the benefit of priority under 35 U.S.C. § 119 from Japanese Patent Application No. 2020-005292, filed Jan. 16, 2020, the entire contents of each of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a technology for controlling a nonvolatile memory. BACKGROUND Memory systems implemented with nonvolatile memories have recently become widespread. As such memory systems, a solid state drive (SSD) implemented with a NAND flash memory has been known. The memory systems such as the SSD are used as storage devices for various host computing systems, such as a server of a data center. In the memory systems such as the SSD, implement of a new technology capable of effectively using storage regions of a nonvolatile memory is required. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a relationship between a memory system according to an embodiment and a host. FIG. 2 is a block diagram illustrating a configuration example of the memory system according to the embodiment. FIG. 3 is a block diagram illustrating a relationship between a plurality of quad-level cell blocks (QLC blocks) used as user data storage regions and a shared flash buffer shared by the plurality of QLC blocks. FIG. 4 is a block diagram illustrating a QLC buffer used as the shared flash buffer. FIG. 5 is a block diagram illustrating a single-level cell buffer (SLC buffer) used as the shared flash buffer. FIG. 6 is a block diagram illustrating a relationship between a plurality of channels and a plurality of NAND flash memory dies used in the memory system according to the embodiment. FIG. 7 is a diagram illustrating a configuration example of a block group (super block) used in the memory system according to the embodiment. FIG. 8 is a diagram for explaining an operation for writing data to a QLC block in a mode for writing 4 bits per memory cell. FIG. 9 is a diagram for explaining an operation for controlling the QLC blocks and the shared flash buffer, which is performed in the memory system according to the embodiment. FIG. 10 is a diagram for explaining an operation for controlling a QLC buffer used as the shared flash buffer. FIG. 11 is a diagram for explaining an operation for controlling an SLC buffer used as the shared flash buffer. FIG. 12 is a diagram for explaining a hybrid SLC buffer using both a static SLC buffer and a dynamic SLC buffer. FIG. 13 is a diagram for explaining an operation for controlling the hybrid SLC buffer. FIG. 14 is a block diagram illustrating a write operation performed in the memory system according to the embodiment. FIG. 15 is a block diagram illustrating an example of a sequence of a write operation and a sequence of a read operation, which are performed in the memory system according to the embodiment. FIG. 16 is a block diagram illustrating another example of the sequence of the write operation and the sequence of the read operation, which are performed in the memory system according to the embodiment. FIG. 17 is a flowchart illustrating a procedure of a write operation performed in the memory system of the embodiment and a procedure of an operation for causing a QLC block in an opened state to transition to a closed state. FIG. 18 is a flowchart illustrating a procedure of an operation for controlling the hybrid SLC buffer. FIG. 19 is a flowchart illustrating a procedure of an operation for reopening a QLC block in a closed state. FIG. 20 is a diagram for explaining a capacity of an SLC buffer required for an SSD of a comparative example and a capacity of the SLC buffer required for the memory system of the embodiment. DETAILED DESCRIPTION Various embodiments will be described hereinafter with reference to the accompanying drawings. In general, according to one embodiment, a memory system is connectable to a host. The memory system comprises a nonvolatile memory including a plurality of blocks, a buffer, and a controller electrically connected to the nonvolatile memory and the buffer. Each of the plurality of blocks is a unit for a data erase operation. The plurality of blocks include a plurality of first blocks and at least one second block. The controller performs a first operation a plurality of times for each of the plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While the second block is not a defective block, the controller performs a second ope