US-12619359-B2 - Memory controller including arbiter, memory system and operation method of the memory controller

US12619359B2US 12619359 B2US12619359 B2US 12619359B2US-12619359-B2

Abstract

A memory controller includes: a request buffer storing read and write requests of a first rank, and read and write requests of a second rank; an arbiter determining a first request and second requests among the stored requests, the second requests to be issued after the first request according to a descending priority, such that a B request has a higher priority than a C request among the second requests; and a command generator generating commands to be issued to the first rank and the second rank according to the issue order of the first and second requests, wherein the B request is a command whose type and rank are different from those of the first request, and wherein the C request is a command whose type is the same as the type of the first request and whose rank is different from the rank of the first request.

Inventors

Jung Hyun Kwon
Min Seob Lee

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260505
Application Date: 20230206
Priority Date: 20221013

Claims (11)

1 . A memory controller, comprising: a request buffer suitable for storing a read request and a write request of a first rank associated with operations of a first memory, and a read request and a write request of a second rank associated with operations of a second memory; an arbiter suitable for determining a first request and second requests among the stored requests, the second requests to be issued after the first request and to be issued according to a descending priority, wherein A, B, C and D requests of the second requests have sequentially descending priorities; and a command generator suitable for generating commands to be issued to the first rank for the operations of the first memory and the second rank for the operations of the second memory according to the issue order of the first and second requests, wherein the A request is a first highest priority command whose type and rank are the same as a type and a rank of the first request, wherein the B request is a second highest priority command, of lower priority than the A request and issued after the A request, whose type and rank are different from the type and rank of the first request, and wherein the C request is a third highest priority command, of lower priority than the B request and issued after the B request, whose type is the same as the type of the first request and whose rank is different from the rank of the first request, and wherein the D request is a fourth highest priority command, of lower priority than the C request and issued after the C request, whose type is different from the type of the first request and whose rank is the same as the rank of the first request.
2 . The memory controller of claim 1 , further comprising: a host interface suitable for receiving the requests from a host; and a memory interface suitable for transferring the commands to the first a-memory of the first rank and the second a memory of the second rank.
3 . A memory system, comprising: a first rank associated with operations of a first memory; a second rank associated with operations of a second memory; and a memory controller suitable for controlling the memories of the first rank and the memories of the second rank, wherein the memory controller includes: a request buffer suitable for storing a read request and a write request of the first rank, and a read request and a write request of the second rank transferred from a host; an arbiter suitable for determining a first request and second requests among the stored requests, the second requests to be issued after the first request and to be issued according to a descending priority, wherein A, B, C and D requests of the second requests have sequentially descending priorities; and a command generator suitable for generating commands to be issued to the first rank for the operations of the first memory and the second rank for the operations of the second memory according to the issue order of the first and second requests, wherein the A request is a first highest priority command whose type and rank are the same as a type and a rank of the first request, wherein the B request is a second highest priority command, of lower priority than the A request and issued after the A request, whose type and rank are different from the type and rank of the first request, wherein the C request is a third highest priority command, of lower priority than the B request and issued after the B request, whose type is the same as the type of the first request and whose rank is different from the rank of the first request, and wherein the D request is a fourth highest priority command, of lower priority than the C request and issued after the C request, whose type is different from the type of the first request and whose rank is the same as the rank of the first request.
4 . The memory system of claim 3 , wherein the memory controller further includes: a host interface suitable for receiving the requests from the host; and a memory interface suitable for transferring the commands to the first rank and the second rank.
5 . A method for operating a memory controller, comprising: determining an issue order of a first request among requests; confirming, among remaining requests, presence of A, B, C and D requests; and giving descending priorities to the A request, the B request, the C request, and the D request, wherein the A request is a first highest priority command whose type and rank are the same as a type and a rank of the first request associated with operations of a first memory, wherein the B request is a second highest priority command, of lower priority than the A request and issued after the A request, whose type and rank associated with operations of a second memory are different from the type and rank of the first request, wherein the C request is a third highest priority command, of lower priority than the B request and issued after the B request, whose type is the same as the type of the first request and whose rank associated with operations of a second memory is different from the rank of the first request, and wherein the D request is a fourth highest priority command, of lower priority than the C request and issued after the C request, whose type is different from the type of the first request and whose rank is the same as the rank of the first request.
6 . The method of claim 5 , further comprising determining one among the remaining requests as a second request which is to be issued after the first request based on the priority.
7 . The method of claim 6 , further comprising receiving the first request, the A request, the B request, the C request, and the D request from a host, before the determining of the issue order of the first request.
8 . The method of claim 7 , further comprising, after the determining of the second request: issuing a command corresponding to the first request; and issuing a command corresponding to the second request.
9 . A method for operating a memory controller, comprising: determining an issue order of a first request, which is a write request of a first rank associated with operations of a first memory; confirming presence of A, B, C, D and E requests, wherein the A request is a write request of the first rank, the B request is a read request of a second rank associated with operations of a second memory, the C request is a write request of the second rank, the D request is a read request of the first rank, and the E request is a write request of the first rank; selecting the A request as a second request to be issued after the first request; selecting the B request, of lower priority than the A request, as a third request to be issued after the second request; and selecting the E request, of lower priority than the B request, as a fourth request to be issued after the third request.
10 . The method of claim 9 , further comprising: selecting the C request as a fifth request to be issued after the fourth request.
11 . The method of claim 9 , further comprising: selecting the D request as a sixth request to be issued after the fifth request.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority of Korean Patent Application No. 10-2022-0131408, filed on Oct. 13, 2022, which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Various embodiments of the present invention relate to a memory controller, and a memory system including the same. 2. Description of the Related Art A memory controller controls read and write operations of a memory according to a request from a host. When the memory operates according to the order of the requests from the host, the performance of the memory system may be inevitably deteriorated. Therefore, it is necessary to perform scheduling in order to improve the performance of the memory system. In particular, since recent memories of memory systems are formed in multiple ranks, it is required to develop an efficient scheduling method that considers even switching between ranks. SUMMARY Embodiments of the present invention are directed to a technology capable of increasing the performance of a memory system. In accordance with an embodiment of the present invention, a memory controller includes: a request buffer suitable for storing a read request and a write request of a first rank, and a read request and a write request of a second rank; an arbiter suitable for determining a first request and second requests among the stored requests, the second requests to be issued after the first request and to be issued according to a descending priority, such that a B request has a higher priority than a C request among the second requests; and a command generator suitable for generating commands to be issued to the first rank and the second rank according to the issue order of the first and second requests, wherein the B request is a command whose type and rank are different from the type and rank of the first request, and wherein the C request is a command whose type is the same as the type of the first request and whose rank is different from the rank of the first request. In accordance with another embodiment of the present invention, a memory system includes: a first rank including one or more memories; a second rank including one or more memories; and a memory controller suitable for controlling the memories of the first rank and the memories of the second rank, wherein the memory controller includes: a request buffer suitable for storing a read request and a write request of the first rank, and a read request and a write request of the second rank transferred from a host; an arbiter suitable for determining a first request and second requests among the stored requests, the second requests to be issued after the first request and to be issued according to a descending priority, such that A, B, C and D requests sequentially have descending priorities among the second requests; and a command generator suitable for generating commands to be issued to the first rank and the second rank according to the issue order the first and second requests, wherein the A request is a command whose type and rank are the same as a type and a rank of the first request, wherein the B request is a command whose type and rank are different from the type and rank of the first request, wherein the C request is a command whose type is the same as the type of the first request and whose rank is different from the rank of the first request, and wherein the D request is a command whose type is different from the type of the first request and whose rank is the same as the rank of the first request. In accordance with another embodiment of the present invention, a method for operating a memory controller includes: determining an issue of a first request among requests; confirming, among remaining requests, presence of A, B, C and D requests; and giving descending priorities to the A request, the B request, the C request, and the D request in a mentioned order, wherein the A request is a command whose type and rank are the same as a type and a rank of the first request, wherein the B request is a command whose type and rank are different from the type and rank of the first request, wherein the C request is a command whose type is the same as the type of the first request and whose rank is different from the rank of the first request, and wherein the D request is a command whose type is different from the type of the first request and whose rank is the same as the rank of the first request. In accordance with another embodiment of the present invention, a method for operating a memory controller includes: determining an issue of a first request, which is a write request of a first rank; confirming presence of an A request, which is a write request of the first rank, and a B request, which is a read request of a second rank, where the A request and the B request are not scheduled; and selecting the A request as a second request to be issued after the first request. In accordance with another embodiment of the