US-12619362-B2 - Memory system and control method

US12619362B2US 12619362 B2US12619362 B2US 12619362B2US-12619362-B2

Abstract

A memory system includes a non-volatile memory configured to store an error correction codes and a memory controller. The memory controller is configured to obtain read information from the non-volatile memory, perform a first decoding process on the read information to output a plurality of decoding results respectively corresponding to a plurality of elements provided in the read information, perform a cancellation process for returning the decoding results satisfying a condition among the plurality of decoding results to values prior to decoding in response to the first decoding process being not successful, and perform a second decoding process using the plurality of decoding results after performing the cancelation process.

Inventors

Takahiro Kubota
Hironori Uchikawa

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260505
Application Date: 20240205
Priority Date: 20230208

Claims (12)

1 . A memory system comprising: a non-volatile memory configured to store an error correction code; and a memory controller configured to obtain read information having a plurality of read elements from the non-volatile memory, perform a first decoding process on the read information to output a plurality of decoding results respectively corresponding to the plurality of elements, perform a cancellation process for returning the decoding results satisfying a condition among the plurality of decoding results to values by deleting correction information indicating an error position calculated through the error correction code, prior to decoding in response to the first decoding process being not successful, and perform, after performing the cancellation process, a second decoding process using the plurality of decoding results, wherein the error correction code is an N-dimensional error correction code in which at least one symbol among symbols of a code is protected by N component code groups (N is an integer of 2 or more), the plurality of elements are M component codes (1≤i≤N, where ni is the number of component codes provided in a component code group of an i-th dimension, and Mis the sum of ni), and the first decoding process includes decoding the M component codes and outputting the reliability of each of the plurality of decoding results respectively corresponding to the plurality of component codes, and wherein the memory controller is further configured to execute the cancellation process when the number of component codes whose reliability is equal to or higher than a fourth threshold value is equal to or greater than a fifth threshold value.
2 . The memory system according to claim 1 , wherein the memory controller is configured to perform the first decoding process on the read information and output the plurality of decoding results and reliability of each of the plurality of decoding results, and the condition indicates that the reliability is less than a first threshold value.
3 . The memory system according to claim 1 , wherein the condition indicates that a distance to each of the plurality of corresponding elements is equal to or greater than a second threshold value.
4 . The memory system according to claim 1 , wherein the error correction code is an N-dimensional error correction code in which at least one symbol among symbols of a code is protected by N component code groups (N is an integer of 2 or more), the plurality of elements are M component codes (1≤i≤N, where ni is the number of component codes provided in a component code group of an i-th dimension, and Mis the sum of ni), the first decoding process includes decoding the M component codes, and the condition provides an indication that, when performing the cancellation process, the number of component codes provided in a component code group of another dimension that changes from a state of successful decoding to a state of unsuccessful decoding is equal to or less than a third threshold value.
5 . The memory system according to claim 1 , wherein the memory controller is configured to select a subset of the decoding results from the plurality of decoding results that satisfy the condition, perform the cancelation process on the subset of decoding results, and perform the second decoding process a plurality of times by using the plurality of decoding results after performing the cancelation process.
6 . The memory system according to claim 1 , wherein the error correction code is a low density parity check code (LDPC), the first decoding process includes decoding the read information using belief propagation, and outputting a log-likelihood ratio of a syndrome corresponding to a check node used in the belief propagation or a minimum value among absolute values of decoding results for a plurality of variable nodes connected to the check node as the reliability of the check node, and the condition provides an indication that the reliability of the check node connected to the variable node corresponding to the decoding result is less than a sixth threshold value.
7 . The memory system according to claim 6 , wherein the memory controller is configured to execute the cancellation process when the number of check nodes whose reliability is equal to or higher than a seventh threshold value is equal to or greater than an eighth threshold value.
8 . The memory system according to claim 1 , wherein the error correction code is a Bose-Chandhuri-Hocquenghem (BCH) code, and the second decoding process is bounded distance decoding for the BCH code.
9 . The memory system according to claim 1 , wherein the error correction code is an N-dimensional error correction code in which at least one symbol among symbols of a code is protected by N component code groups (N is an integer of 2 or more), and the second decoding process is iterative decoding for M component codes (1≤i≤N, where ni is the number of component codes included in a component code group of an i-th dimension, and M is the sum of ni).
10 . A control method performed by a memory controller that controls a non-volatile memory that stores an error correction code, the control method comprising: obtaining read information having a plurality of elements from the non-volatile memory; performing a first decoding process on the read information to output a plurality of decoding results respectively corresponding to the plurality of elements included in the read information, performing a cancellation process for returning the decoding results satisfying a predetermined condition among the plurality of decoding results to values by deleting correction information indicating an error position calculated through the error correction code before the decoding in response to the first decoding process being not successful; and performing, after performing the cancelation process, a second decoding process using the plurality of decoding results; wherein the error correction code is an N-dimensional error correction code in which at least one symbol among symbols of a code is protected by N component code groups (N is an integer of 2 or more), the plurality of elements are M component codes (1≤i≤N, where ni is the number of component codes provided in a component code group of an i-th dimension, and Mis the sum of ni), and the first decoding process includes decoding the M component codes and outputting the reliability of each of the plurality of decoding results respectively corresponding to the plurality of component codes.
11 . The method according to claim 10 , further comprising: performing the first decoding process on the read information and outputting the plurality of decoding results and reliability of each of the plurality of decoding results, wherein the condition indicates that the reliability is less than a first threshold value.
12 . The method according to claim 10 , wherein the condition indicates that a distance to each of the plurality of corresponding elements is equal to or greater than a second threshold value.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-017630, filed Feb. 8, 2023, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a memory system and a control method. BACKGROUND In a memory system, data subjected to error correction coding is generally stored in order to protect data to be stored. For this reason, when data stored in the memory system is read, decoding is performed on the data subjected to error correction coding. DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an operation of protecting data with an error correction code. FIG. 2 is a diagram showing an example of a product code. FIG. 3 is a block diagram showing an example of functional blocks that execute turbo decoding on a two-dimensional error correction code. FIG. 4 is a flowchart of a processing flow according to the functional blocks shown in FIG. 3. FIG. 5 is a block diagram of a memory system according to a first embodiment. FIG. 6 is a diagram showing an example of an outer code and an inner code. FIG. 7 is a block diagram of a decoder according to the first embodiment. FIG. 8 is a block diagram of a SISO decoding unit according to the first embodiment. FIG. 9 is a flowchart of decoding processing performed by the memory system according to the first embodiment. FIG. 10 is a diagram showing cancellation processing. FIG. 11 is a diagram showing an example in which a syndrome value of a component code changes from a satisfied state to an unsatisfied state. FIG. 12 is a diagram showing an example in which a syndrome value of a component code remains in an unsatisfied state. FIG. 13 is a block diagram of a decoder according to a second embodiment. FIG. 14 is a diagram showing cancellation processing. DETAILED DESCRIPTION Embodiments provide a memory system and a control method which are capable of executing error correction (decoding) with higher accuracy. In general, according to one embodiment, a memory system includes a non-volatile memory configured to store an error correction codes and a memory controller. The memory controller is configured to obtain read information having a plurality of read elements from the non-volatile memory, perform a first decoding process on the read information to output a plurality of decoding results respectively corresponding to the plurality of elements, perform a cancellation process for returning the decoding results satisfying a condition among the plurality of decoding results to values prior to decoding in response to the first decoding process being not successful, and perform, after performing the cancellation process, a second decoding process using the plurality of decoding results. A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings. The present disclosure is not limited to the following embodiments. In recent years, memory systems using non-volatile memories such as a NAND flash memory (hereinafter simply referred to as a NAND memory) have been used in various places due to their high speed characteristics. However, data read from the non-volatile memory is likely to include errors caused by an elapsed time since the data is stored in the non-volatile memory, noise generated during reading/writing, or the like. For this reason, in general, data stored in the non-volatile memory is encoded using an error correction code, and the data is decoded using the error correction code at the time of reading, thereby removing errors provided in the read data. FIG. 1 is a diagram showing an operation of protecting data with an error correction code in a memory system according to a comparative example. A user 931 and a user 932 may each be an information processing device such as a personal computer, a server device, a portable information apparatus, a digital still camera, or the like. The user 931 transmits data to be written (hereinafter referred to as write data) to a memory system 900. The memory system 900 encodes the write data received from the user 931 using an encoder 941, and writes the encoded data (code word) generated thereby to a non-volatile memory 920. Thus, the encoded data written to the non-volatile memory 920 does not basically include an error. The encoded data stored in the non-volatile memory 920 is read in response to, for example, a read request from the user 932. Here, there is a possibility that the read encoded data will include an error. Consequently, decoding is executed while removing the error provided in the read encoded data using a decoder 942, thereby restoring the original code word. Thereafter, the original code word or the restored write data before encoding is transmitted to the user 932. The user 932 that issues the read request may be the same user as the user 931 who issues the write request, or may be a different