US-12619363-B2 - Storage device that inputs additional command during read data output time and operating method thereof

US12619363B2US 12619363 B2US12619363 B2US 12619363B2US-12619363-B2

Abstract

A storage device may include a memory and a controller. The controller may input, to the memory, a read command for a first plane among the plurality of planes through a first path connected to the first terminal, receive, from the memory, read data for the read command through a second path connected to the second terminal, and input, to the memory, one or more additional commands through the first path in parallel with an operation of receiving the read data during an expected output time of the read data.

Inventors

Hye Rim HYUN
Seung Gu JI

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260505
Application Date: 20240612
Priority Date: 20240205

Claims (11)

1 . A storage device comprising: a memory including a plurality of planes, a first terminal for inputting one or more commands, and a second terminal for inputting or outputting data; and a controller configured to: input, to the memory, a read command for a first plane among the plurality of planes through a first path connected to the first terminal, receive, from the memory, read data for the read command through a second path connected to the second terminal, and input, to the memory, additional commands through the first path in parallel with an operation of receiving the read data during an expected output time of the read data, wherein the additional commands include a read status command for a second plane among the plurality of planes and a read sensing command for a third plane among the plurality of planes, and in response to the read sensing command, read data from memory cells of the third plane is temporarily stored into a data buffer for subsequent outputting from the memory.
2 . The storage device according to claim 1 , wherein the controller is configured to determine the expected output time based on an interface speed for the second path and a size of the read data.
3 . The storage device according to claim 1 , wherein the controller is configured to determine the expected output time based on a size of the read data, and a number of toggles per time of a data strobe signal input to the memory.
4 . The storage device according to claim 1 , wherein the second plane and the third plane are adjacent to the first plane.
5 . The storage device according to claim 1 , wherein the additional commands include at least one of a command for setting a feature of the memory, a command for acquiring the feature of the memory, a reset command for resetting the memory, and a command for reading identification information of the memory.
6 . An operating method of a storage device, the operating method comprising: inputting, to a memory, a read command for a first plane among a plurality of planes of the memory through a first path connected to a first terminal of the memory; and executing, in parallel, an operation of receiving, from the memory, read data for the read command through a second path connected to a second terminal of the memory, and an operation of inputting, to the memory, additional commands through the first path during an expected output time of the read data, wherein the additional commands include a read status command for a second plane among the plurality of planes and a read sensing command for a third plane among the plurality of planes, and in response to the read sensing command, read data from memory cells of the third plane is temporarily stored into a data buffer for subsequent outputting from the memory.
7 . The method according to claim 6 , wherein the expected output time is determined based on an interface speed for the second path and a size of the read data.
8 . The method according to claim 6 , wherein the expected output time is determined based on a size of the read data, and a number of toggles per time of a data strobe signal input to the memory.
9 . The method according to claim 6 , wherein the second plane and the third plane are adjacent to the first plane.
10 . The method according to claim 6 , wherein the additional commands include at least one of a command for setting a feature of the memory, a command for acquiring the feature of the memory, a reset command for resetting the memory, and a command for reading identification information of the memory.
11 . A storage device comprising: a memory including a first terminal, a second terminal, and a plurality of planes including a first plane; a first path coupled to the first terminal; a second path coupled to the second terminal and separated from the first path; and a controller coupled to the memory through the first and second paths, wherein the controller is configured to: transmit, to the memory, a read command for the first plane through the first path, and during an expected output time, simultaneously perform receiving, from the memory, read data for the read command through the second path, and transmitting, to the memory, additional commands through the first path, and wherein the expected output time is determined based on a size of the read data, and at least one of an interface speed of the second path and a number of toggles per time of a data strobe signal transmitted to the memory, wherein the additional commands include a read status command for a second plane among the plurality of planes and a read sensing command for a third plane among the plurality of planes, and in response to the read sensing command, read data from memory cells of the third plane is temporarily stored into a data buffer for subsequent outputting from the memory.

Description

CROSS-REFERENCES TO RELATED APPLICATION The present application claims priority under 35 U.S.C. 119(a) to Korean patent application number 10-2024-0017129 filed on Feb. 5, 2024, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Various embodiments of the present disclosure generally relate to a storage device that inputs an additional command during read data output time and an operating method thereof. 2. Related Art A storage device is a device for storing data according to a request from an external device such as a computer, a mobile terminal (e.g., a smart phone or tablet), or the like. A storage device may include a memory for storing data therein and a controller for controlling the memory. The memory may be a volatile memory or a non-volatile memory. The controller may receive a command from an external device (i.e., a host), and execute or control operations to read, write, or erase data in the memory included in the storage device according to the received command. Conventional storage device uses a common path for command input and data input and output (input/output). Therefore, while data is being output from the memory, the controller cannot input command to the memory. SUMMARY Various embodiments of the present disclosure are directed to provide a storage device capable of preventing unnecessary performance degradation through effective command scheduling when the path used for command input and the path used for data input/output are separated, and an operating method thereof. In an embodiment of the present disclosure, a storage device may include a memory including a plurality of planes, a first terminal for inputting one or more commands, and a second terminal for inputting or outputting data; and a controller configured to input, to the memory, a read command for a first plane among the plurality of planes through a first path connected to the first terminal, receive, from the memory, read data for the read command through a second path connected to the second terminal, and input, to the memory, one or more additional commands through the first path in parallel with an operation of receiving the read data during an expected output time of the read data. In another embodiment of the present disclosure, an operating method of a storage device may include inputting, to a memory, a read command for a first plane among a plurality of planes of the memory through a first path connected to a first terminal of the memory; and executing, in parallel, an operation of receiving, from the memory, read data for the read command through a second path connected to a second terminal of the memory, and an operation of inputting, to the memory, one or more additional commands through the first path during an expected output time of the read data. In another embodiment of the present disclosure, a storage device may include a memory including a first terminal, a second terminal, and a plurality of planes including a first plane; a first path coupled to the first terminal; a second path coupled to the second terminal and separated from the first path; and a controller coupled to the memory through the first and second paths. The controller may transmit, to the memory, a read command for a first plane through the first path, and during an expected output time, simultaneously perform receiving, from the memory, read data for the read command through the second path, and transmitting, to the memory, at least one additional command through the first path. The expected output time may be determined based on a size of the read data, and at least one of an interface speed of the second path and the number of toggles per time of a data strobe signal transmitted to the memory. According to embodiments of the present disclosure, it is possible to prevent unnecessary performance degradation through effective command scheduling when the path used for command input and the path used for data input/output are separated. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure. FIG. 2 is a block diagram schematically illustrating a memory of FIG. 1. FIG. 3 is a diagram showing schematic structure of a storage device according to an embodiment of the present disclosure. FIG. 4 is a diagram showing an operation in which a controller inputs a read command into a memory according to an embodiment of the present disclosure. FIG. 5 is a diagram showing an operation in which a controller receives read data for a read command from a memory according to an embodiment of the present disclosure. FIG. 6 is a diagram showing an operation in which a controller inputs one or more additional commands to a memory according to an embodiment of the present disclosure. FIG. 7 is a diagram showing status of a first path and a second path over time according to an embodiment of the present disclosure. FIG. 8 is a