US-12619373-B2 - Memory device and method for monitoring the performances of a memory device

Abstract

The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Inventors

• Alberto Troia
• Antonino Mondello

Assignees

• LODESTAR LICENSING GROUP LLC

Dates

Publication Date

20260505

Application Date

20241126

Claims (20)

1. 1 . A non-volatile memory device including an array of memory cells with associated decoding and sensing circuitry and a memory controller, wherein the memory array comprises: a plurality of sub-arrays; a first plurality of first memory blocks in each sub-array; and a dummy row for each first memory block for storing internal block variables of a reading phase and a known pattern, wherein the memory controller is configured to: update content of the dummy row, for a portion of a second plurality of memory blocks comprising a second memory block, in response to the portion of the second plurality of memory blocks being subject to same environmental variation conditions as the first memory block; and trim parameters of the reading based on the updated content.
2. 2 . The non-volatile memory device of claim 1 , wherein the trimmed parameters correspond to a set temperature value recorded in a programmable register.
3. 3 . The non-volatile memory device of claim 1 , wherein the parameters include voltage values.
4. 4 . The non-volatile memory device of claim 1 , wherein the parameters include timing used in an erase algorithm.
5. 5 . The non-volatile memory device of claim 1 , wherein the parameters to be trimmed are selected after having performed a reading of the known pattern stored in the dummy row.
6. 6 . The non-volatile memory device of claim 1 , wherein the memory controller is configured to read the dummy row for each first memory block when the memory device is isolated from an external environment.
7. 7 . The non-volatile memory device of claim 1 , wherein the memory controller to update the content comprises the memory controller storing in the dummy row for each first memory block new internal block variables including reading pulses applied to a memory block of the first plurality of memory blocks during the reading phase.
8. 8 . A system, comprising: a host device; a non-volatile memory device coupled to the host device and comprising at least an array of memory cells with associated decoding and sensing circuitry and a memory controller, a plurality of sub-arrays in the memory array; a plurality of memory blocks in each sub-array; and a dummy row for each memory block for storing internal block variables of a reading phase and a known pattern, wherein a first dummy row of a first memory block is provided in each of a plurality of different memory blocks of a first one of the plurality of subarrays, and wherein the memory controller is configured to: update content of the first dummy row periodically; and update the content, for a portion of the plurality of different memory blocks, in response to the portion being subject to same environmental variation conditions as the first memory block.
9. 9 . The system of claim 8 , comprising storing the known pattern in the memory controller.
10. 10 . The system of claim 8 , wherein the internal block variables comprise target voltages applied during the reading phase.
11. 11 . The system of claim 8 , wherein the internal block variables comprise reading pulses applied during the reading phase.
12. 12 . The system of claim 8 , wherein the memory controller is configured to: retrieve the internal block variables of a previous reading phase from each dummy row; and start the reading phase of each memory block based at least in part on the internal block variables of the previous reading phase.
13. 13 . The system of claim 8 , wherein the memory controller is configured to write a different known pattern to at least one of the respective dummy rows.
14. 14 . A method for checking the status of a non-volatile memory device including an array of memory cells including memory blocks and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing, in a dummy row, internal block variables and a known pattern; performing a reading of the dummy row; comparing the result of the reading with the known pattern; and trimming parameters of the reading set for a next erase operation based at least in part on a result of the comparing and on drift information of the known pattern.
15. 15 . The method of claim 14 , comprising retrieving the internal block variables of a previous erasing from the dummy row.
16. 16 . The method of claim 14 , comprising storing the known pattern in the dummy row during electrical wafer sort, during electrical testing, or both.
17. 17 . The method of claim 14 , comprising trimming the parameters at different temperatures.
18. 18 . The method of claim 14 , comprising trimming the parameters at different aging points of the non-volatile memory device.
19. 19 . The method of claim 14 , comprising automatically performing the method responsive to a triggering event.
20. 20 . The method of claim 14 , comprising: storing a different known pattern in the dummy row; and storing the known pattern and the different known pattern in the memory controller.

Description

PRIORITY INFORMATION This application is a Continuation of U.S. application Ser. No. 18/482,539, filed Oct. 6, 2023, which is a Continuation of U.S. application Ser. No. 17/961,373, filed Oct. 6, 2022, which issued as U.S. Pat. No. 11,782,633 on Oct. 10, 2023, which is a Continuation of U.S. application Ser. No. 16/624,512, filed on Dec. 19, 2019, which issued as U.S. Pat. No. 11,467,761 on Oct. 11, 2022, which is a U.S. National Stage Application under 35 U.S.C. § 371 of International Application Number PCT/IB2019/000451, filed on May 31, 2019, the contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure generally relates to memory devices, and more particularly relates to methods for setting operating parameters of an integrated memory circuit. More particularly, the present disclosure relates to a memory device and a corresponding method for self trimming operating parameters of a memory device and for monitoring the performances and healthiness of the memory device. BACKGROUND Memory devices are well known in the electronic field to store and allow accessing to digital information. In general, different kind of semiconductor memory devices may be incorporated into more complex systems including non-volatile memory components and/or volatile memory components, for instance in so-called System-on-Chips (SoC) wherein the above-mentioned memory components are embedded. Nowadays, however, the need of Real Time Operative Systems, in particular for automotive applications requires SoC with more and more increased performances and efficiency and the known solutions no longer satisfy these requirements. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory or NOR flash memory, among others. NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash. An important feature of a flash memory is the fact that it can be erased in blocks instead of one byte at a time. However, one key disadvantage of flash memory is that it can only endure a relatively small number of write and erase cycles in a specific block. Flash memory devices can include large arrays of memory cells for storing data, frequently organized into rows and columns. Individual memory cells and/or ranges of memory cells can be addressed by their row and column. When a memory array is addressed, there may be one or more layers of address translation, to e.g., translate between a logical address utilized by a host device (i.e. the SoC) and a physical address corresponding to a location in the memory array. Although uncommon, it is possible for the address information provided to a memory device on a command/address bus thereof to be corrupted by an error, such that an internal operation of the memory device (e.g., a read operation, a write operation, an erase operation, etc.) can be performed on a different physical address than was targeted by a host device or a controller of the memory device. Accordingly, a way to verify that a memory operation has been performed at the intended address is required and the present disclosure is focused on methods for checking the correctness of the reading phase. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a schematic view of a system including a memory component associated to a controller exchanging data, address and control signals with the memory device; FIG. 2 is a schematic view of the memory component according to the present disclosure; FIG. 3 is a schematic layout view of an example of the memory component according to embodiments of the present disclosure; FIG. 4 is a schematic view of a memory block formed by a plurality of rows of the memory array according to one embodiment of the present disclosure; FIG. 5 is a schematic view of a group of address registers for a memory page in the memory component of the present disclosure. FIG. 6 shows in a schematic diagram the distribution of a correctly erased/programmed cell (1 bit/cell); FIG. 7 shows a diagram corresponding to FIG. 6 reporting an enlarged distribution shifted toward the depletion state (negative Vth) due to aging, temperature and stress; FIG. 8 shows in block diagram an example of the method steps of the present disclosure. DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be disclosed and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. Several embodiments of the present disclosure are directed to memory devices, system