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US-12619380-B2 - Solving submission queue entry overflow with shadow submission queue

US12619380B2US 12619380 B2US12619380 B2US 12619380B2US-12619380-B2

Abstract

A memory is disclosed. The memory may include a first data structure. The first data structure may include a first field to store a first data relating to a command. The memory may also include a second data structure. The second data structure may include a second field to store a second data relating to the command. A first queue stored in the memory may include the first data structure. A second queue stored in the memory may include the second data structure.

Inventors

  • Daniel Lee HELMICK
  • Robert Wayne Moss
  • Michael Allison
  • Sumanth Jannyavula Venkata
  • Judith Rose BROCK

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260505
Application Date
20230728

Claims (15)

  1. 1 . A memory, comprising: a first data structure stored in the memory, the first data structure including a first field to store a first data relating to a command; a second data structure stored in the memory, the second data structure including a second field to store a second data relating to the command; a first queue stored in the memory, the first queue including the first data structure, the first queue including a first relative ordering of the first data structure and a third data structure storing a third data relating to a second command; and a second queue stored in the memory, the second queue including the second data structure, the second queue including a second relative ordering of the second data structure and a fourth data structure storing a fourth data relating to the second command, wherein the first queue is a first submission queue and the second queue is a second submission queue, or the first queue is a first completion queue and the second queue is a second completion queue wherein the second relative ordering parallels the first relative ordering, and wherein a controller is configured to process the command based at least in part on the first data relating to the command and the second data relating to the command.
  2. 2 . The memory according to claim 1 , wherein: the first queue includes a number of entries; and the second queue includes the number of entries.
  3. 3 . The memory according to claim 2 , wherein: the first data structure is located at a position in the first queue; and the second data structure is located at a same position in the second queue.
  4. 4 . The memory according to claim 1 , wherein: the first queue includes a first number of entries; and the second queue includes a second number of entries, wherein the second number of entries is less than the first number of entries.
  5. 5 . The memory according to claim 4 , wherein the first data structure includes a third field to store an identifier of the second data structure.
  6. 6 . The memory according to claim 4 , wherein the second data structure includes a phase value.
  7. 7 . A method, comprising: establishing a first data structure by a processor, the first data structure including a first field storing a first data relating to a command; establishing a second data structure by the processor, the second data structure including a second field storing a second data related to the command; storing the first data structure in a first queue in a memory by the processor, the first queue including a first relative ordering of the first data structure and a third data structure storing a third data relating to a second command; and storing the second data structure in a second queue in the memory by the processor, the second queue including a second relative ordering of the second data structure and a fourth data structure storing a fourth data relating to the second command, wherein the first queue is a first submission queue and the second queue is a second submission queue, or the first queue is a first completion queue and the second queue is a second completion queue, and wherein the second relative ordering parallels the first relative ordering.
  8. 8 . The method according to claim 7 , wherein establishing the first data structure by the processor includes storing a value in a third field in the first data structure to indicate the presence of the second data structure in the memory.
  9. 9 . The method according to claim 7 , wherein: establishing the first data structure by the processor includes storing an operation code (opcode) or a command identifier in a third field in the first data structure; and establishing the second data structure by the processor includes storing the opcode or the command identifier in a fourth field in the second data structure.
  10. 10 . The method according to claim 7 , wherein: the first queue includes a number of entries; and the second queue includes the number of entries.
  11. 11 . The method according to claim 10 , wherein: the first data structure is located at a position in the first queue; and the second data structure is located at a same position in the second queue.
  12. 12 . The method according to claim 7 , wherein: the first queue includes a first number of entries; and the second queue includes a second number of entries, wherein the second number of entries is less than the first number of entries.
  13. 13 . The method according to claim 12 , wherein establishing a first data structure by a processor includes storing an identifier of the second data structure in a third field in the first data structure.
  14. 14 . The method according to claim 12 , wherein the second data structure includes a phase value.
  15. 15 . The method according to claim 7 , wherein: the method further comprises: requesting a format for the second data structure from a storage device by the processor; and receiving the format for the second data structure from the storage device by the processor; and establishing the second data structure by the processor includes establishing the second data structure by the processor based at least in part on the format for the second data structure received from the storage device by the processor.

Description

RELATED APPLICATION DATA This application claims the benefit of U.S. Patent Application Ser. No. 63/427,415, filed Nov. 22, 2022, and U.S. Provisional Patent Application Ser. No. 63/427,410, filed Nov. 22, 2022, both of which are incorporated by reference herein for all purposes. This application is related to U.S. patent application Ser. No. 18/227,897, filed Jul. 28, 2023, which claims the benefit of U.S. Provisional Patent Application Ser. No. 63/427,407, filed Nov. 22, 2022, both of which are incorporated by reference for all purposes. This application is related to U.S. patent application Ser. No. 18/227,902, filed Jul. 28, 2023, which claims the benefit of U.S. Provisional Patent Application Ser. No. 63/453,754, filed Mar. 21, 2023, U.S. Provisional Patent Application Ser. No. 63/427,422, filed Nov. 22, 2022, and U.S. Provisional Patent Application Ser. No. 63/427,420, filed Nov. 22, 2022, all of which are incorporated by reference herein for all purposes. FIELD The disclosure relates generally to storage devices, and more particularly to increasing the amount of data that may be included with a submission queue entry. BACKGROUND Hosts submit commands to storage devices using submission queues. A typical submission queue entry includes 64 bytes of data. Fields in the submission queue entries include, for example, an identifier for the command and the logical block address of the data, among other possibilities. But as the amount of data included in a submission queue entry, particularly information that is included in a standard, has grown, the space available for additional information that might be provided by the host has shrunk. Soon, almost every bit in a submission queue entry may be used, leaving no room for additional data that a host might want to include in a submission queue entry. A need remains to support including additional data in a submission queue entry. BRIEF DESCRIPTION OF THE DRAWINGS The drawings described below are examples of how embodiments of the disclosure may be implemented, and are not intended to limit embodiments of the disclosure. Individual embodiments of the disclosure may include elements not shown in particular figures and/or may omit elements shown in particular figures. The drawings are intended to provide illustration and may not be to scale. FIG. 1 shows a machine including a processor and storage device to support submission queue entries for commands sent to the storage device, according to embodiments of the disclosure. FIG. 2 shows details of the machine of FIG. 1, according to embodiments of the disclosure. FIG. 3 shows details of the storage device of FIG. 1, according to embodiments of the disclosure. FIG. 4 shows the process of submitting a command to the storage device of FIG. 1 using a submission queue entry, according to embodiments of the disclosure. FIG. 5 shows details of the submission queue entry of FIG. 4 for a write command to be submitted to the storage device of FIG. 1, according to embodiments of the disclosure. FIG. 6 shows a high-level representation of the submission queue of FIG. 4, according to embodiments of the disclosure. FIG. 7A shows the submission queue of FIG. 4 with a sparse shadow queue to store additional data relating to a command in the submission queue entry of FIG. 4 in the submission queue of FIG. 4, according to embodiments of the disclosure. FIG. 7B shows the submission queue of FIG. 4 with a dense shadow queue to store additional data relating to a command in the submission queue entry of FIG. 4 in the submission queue of FIG. 4, according to embodiments of the disclosure. FIG. 8 shows details of the shadow queue entry of FIGS. 7A-7B in the shadow queues of FIGS. 7A-7B to store additional command data for the submission queue entry of FIG. 4 in the submission queue of FIG. 4, according to embodiments of the disclosure. FIG. 9 shows the processor of FIG. 1 requesting and receiving a log page from the storage device of FIG. 1, for information about the structure of the shadow queue entry of FIG. 8, according to embodiments of the disclosure. FIG. 10 shows a flowchart of an example procedure for the processor of FIG. 1 to establish the submission queue entry of FIG. 4 and the shadow queue entry of FIGS. 7A-7B for additional command data, according to embodiments of the disclosure. FIG. 11 shows a flowchart of an example procedure for the processor of FIG. 1 to assist the storage device of FIG. 1 in pairing the submission queue entry of FIG. 4 with the shadow queue entry of FIGS. 7A-7B, according to embodiments of the disclosure. FIG. 12 shows a flowchart of an example procedure for the processor of FIG. 1 to store the shadow queue entry of FIGS. 7A-7B in the shadow queues of FIGS. 7A-7B, according to embodiments of the disclosure. FIG. 13 shows a flowchart of an example procedure for the processor of FIG. 1 to inform the storage device of FIG. 1 that the submission queue entry of FIG. 4 is present in the submission queue