US-12619382-B2 - Memory controller and storage device including the same

Abstract

A memory controller that includes a buffer memory configured to store user data and a write command corresponding to a write request received from a host, a processor configured to control a memory device to perform a write operation, and a host interface configured to determine an active range based on mapping information of the memory device, determine the throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, and determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host.

Inventors

• Geon Woo KIM
• DAE HOON JANG
• Jhu Yeong Jhin

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260505

Application Date

20230717

Priority Date

20230112

Claims (19)

1. 1 . A memory controller comprising: a buffer memory configured to store user data and a write command corresponding to a write request received from a host; a processor configured to control a memory device to perform a write operation corresponding to the write command; and a host interface configured to: determine an active range based on mapping information of the memory device, determine a throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host.
2. 2 . The memory controller of claim 1 , wherein the host interface determines the delay time of the write completion response by further considering a free capacity of the buffer memory.
3. 3 . The memory controller of claim 1 , wherein the host interface determines the delay time of the write completion response by further considering an amount of one or more commands which are received from the host but not processed by the processor.
4. 4 . The memory controller of claim 1 , wherein the host interface determines the delay time of the write completion response based on Equation 1 below, T = ( BM tt - BM free ) × BL × W_QD ÷ BM tt × c , [ Equation ⁢ 1 ] where T is the delay time, BMtt is the throttle trigger value according to the active range, BMfree is a free capacity of the buffer memory, BL is the base latency according to the write ratio, W_QD is an amount of one or more commands which are not processed by the processor, and c is a calibration constant.
5. 5 . The memory controller of claim 1 , wherein the processor controls the memory device to perform a garbage collection operation on a plurality of memory blocks included in the memory device.
6. 6 . The memory controller of claim 5 , wherein the host interface determines the active range based on a ratio of an area where user data is currently stored to total user data area, when receiving the write request from the host while performing the garbage collection operation.
7. 7 . The memory controller of claim 1 , wherein the host interface determines the throttle trigger value based on linear interpolation of a first throttle trigger value when the active range is a first value and a second throttle trigger value when the active range is a second value.
8. 8 . The memory controller of claim 1 , wherein the host interface determines the base latency based on linear interpolation of a first latency when the write ratio is a first value and a second latency when the write ratio is a second value.
9. 9 . The memory controller of claim 1 , wherein the host interface comprises: a host interface layer (HIL) core configured to determine the delay time of the write completion response; and a command status scheduler configured to delay the write completion response according to the delay time and provide the delayed write completion response to the host.
10. 10 . A storage device comprising: a memory device including a plurality of memory blocks; a buffer memory configured to store user data and a write command corresponding to a write request received from a host; and a memory controller configured to: control the memory device to perform a write operation corresponding to the write command, determine an active range based on mapping data, determine a throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host.
11. 11 . The storage device of claim 10 , wherein the memory controller determines the delay time of the write completion response by further considering a free capacity of the buffer memory.
12. 12 . The storage device of claim 10 , wherein the memory controller determines the delay time of the write completion response by further considering an amount of one or more commands which are received from the host but not processed by the memory controller.
13. 13 . The storage device of claim 10 , wherein the memory controller determines the delay time of the write completion response based on Equation 1 below, T = ( BM tt - BM free ) × BL × W_QD ÷ BM tt × c , [ Equation ⁢ 1 ] where T is the delay time, BMtt is the throttle trigger value according to the active range, BMfree is a free capacity of the buffer memory, BL is the base latency according to the write ratio, W_QD is an amount of one or more commands which are not processed by the processor, and c is a calibration constant.
14. 14 . The storage device of claim 10 , wherein the memory controller controls the memory device to perform a garbage collection operation on the plurality of memory blocks.
15. 15 . The storage device of claim 14 , wherein the memory controller determines the active range based on a ratio of an area where user data is currently stored to total user data area when receiving the write request from the host while performing the garbage collection operation.
16. 16 . The storage device of claim 10 , wherein the memory controller determines the throttle trigger value based on linear interpolation of a first throttle trigger value when the active range is a first value and a second throttle trigger value when the active range is a second value.
17. 17 . The storage device of claim 10 , wherein the memory controller determines the base latency based on linear interpolation of a first latency when the write ratio is a first value and a second latency when the write ratio is a second value.
18. 18 . The storage device of claim 10 , wherein the memory controller comprises: a host interface layer (HIL) core configured to determine the delay time of the write completion response; and a command status scheduler configured to delay write completion response by the delay time and provide the delayed write completion response to the host.
19. 19 . A storage device comprising: a memory device; and a memory controller including a buffer memory and configured to: perform a write operation on the memory device in response to a write request from a host; and transmit, to the host, a write completion response responsive to the write request at a particular time, wherein the particular time is determined based on a throttle trigger value and a base latency, wherein the throttle trigger value is determined based on an active range with reference to mapping data associated with the write operation, and wherein the base latency is determined based on a write ratio of the write command to commands received from the host.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2023-0004815 filed on Jan. 12, 2023, the entire disclosure of which is incorporated by reference herein. BACKGROUND 1. Field of Invention Embodiments of the present disclosure relate to an electronic device, and more particularly, to a storage device including a memory device and a memory controller. 2. Description of Related Art In a storage device, quality of service (QOS) is an item indicating how uniformly each command is processed, and is measured based on command latency. In the past, only throughput, which means an amount of data processed per unit time, was a main factor in evaluating performance of a storage device. However, in the latest server environment, while requiring high throughput, quality of service (for example, command latency) felt by a user is also considered a main factor in evaluating the performance of the storage device. When a host transfers a command at a speed equal to or greater than a processing speed of the storage device, the number of commands that may be simultaneously processed in the storage device may be exceeded. At this time, a phenomenon in which QoS is reduced while latency increases instantaneously may occur. In order to prevent QoS from rapidly being reduced, the storage device may use a throttling technique for delaying the command transferred and received from the host. However, since the throttling technique secures QoS through the delay of the command received from the host and uses a fixed processing function, optimized latency, that is, optimal QoS may not be guaranteed. SUMMARY An embodiment of the present disclosure provides a memory controller supporting an improved throttling technique and a method of operating a storage device including the same. According to an embodiment of the present disclosure, a memory controller may include a buffer memory configured to store user data and a write command corresponding to a write request received from a host, a processor configured to control a memory device to perform a write operation, and a host interface configured to determine an active range based on mapping information of the memory device, determine the throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, and determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host. According to an embodiment of the present disclosure, a storage device may include a memory device including a plurality of memory blocks, a buffer memory configured to store user data and a write command corresponding to a write request received from a host, and a memory controller configured to control the memory device to perform a write operation corresponding to the write command, determine an active range based on mapping data, determine the throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host. According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller including a buffer memory and configured to perform a write operation on the memory device in response to a write request from a host, and transmit, to the host, a write completion response responsive to the write request at a particular time. The particular time may be determined based on a throttle trigger value and a base latency. The throttle trigger value may be determined based on an active range with reference to mapping data associated with the write operation. The base latency may be determined based on a write ratio of the write command to commands received from the host. According to the present technology, a memory controller supporting an improved throttling technique and a method of operating a storage device including the same are provided. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating a command interface operation according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating a memory controller according to an embodiment of the disclosure. FIG. 4 is a diagram illustrating a garbage collection operation according to an embodiment of the present disclosure. FIG. 5 is a diagram illustrating a host interface according to an embodiment of the present disclosure.