US-12619395-B2 - Memory device including ternary memory cell

US12619395B2US 12619395 B2US12619395 B2US 12619395B2US-12619395-B2

Abstract

Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.

Inventors

Kyung Rok Kim
Jae Won Jeong
YOUNGEUN CHOI
Wooseok Kim
Myoung Kim

Assignees

UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Dates

Publication Date: 20260505
Application Date: 20220215
Priority Date: 20210628

Claims (10)

1 . A memory cell in a memory device for a logic-in-memory, the memory cell comprising: a single ternary memory cell configured to store ternary data having a weight value of one of −1, 0 and +1; and a weight cell configured to control a current flowing in an operation line on a basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell comprises a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line, wherein when the ternary memory cell stores the weight value of −1, the weight data of the first node is 0 and the inversed weight data of the second node is 2, when the ternary memory cell stores the weight value of 0, the weight data of the first node and the inversed weight data of the second node are 1, and when the ternary memory cell stores the weight value of +1, the weight data of the first node is 2 and the inversed weight data of the second node is 0.
2 . The memory cell of claim 1 , wherein the first transistor is connected to the first node, the second transistor, and a first operation line, the second transistor is connected to the second node, the first transistor, and a second operation line, and the third transistor is connected to a third node that is a junction of the first transistor and the second transistor, and to the activation line.
3 . The memory cell of claim 2 , wherein the ternary memory cell is configured to: receive the weight data via a first bit line; receive the inversed weight data via a second bit line; and output the weight data and the inversed weight data as the weight cell on a basis of an input signal via a word line.
4 . The memory cell of claim 2 , wherein the weight cell is configured to: receive the weight data and the inversed weight data from the ternary memory cell; receive the activation signal to activate the weight cell via the activation line; and block at least one of a first current path along the first operation line and the first transistor or a second current path along the second operation line and the second transistor, on a basis of the weight data and the inversed weight data.
5 . The memory cell of claim 1 , wherein the memory cell comprises one ternary memory cell and one weight cell.
6 . The memory cell of claim 1 , wherein a number of transistors included in the weight cell is three, and a number of transistors included in the memory cell is nine.
7 . A memory device for a logic-in-memory, the memory device comprising: a memory cell array in which a plurality of memory cells are arranged, each of the plurality of memory cells comprising a single ternary memory cell configured to store ternary data having a weight value of one of −1, 0 and +1 and a weight cell; a decoder connected to the memory cell array via at least one word line and configured to select at least one of the plurality of memory cells; and a read and write circuit connected to the memory cell array via a plurality of bit lines and configured to perform data latch, wherein the weight cell is configured to control a current flowing in an operation line on a basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, and the weight cell comprises a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line, wherein when the ternary memory cell stores the weight value of −1, the weight data of the first node is 0 and the inversed weight data of the second node is 2, when the ternary memory cell stores the weight value of 0, the weight data of the first node and the inversed weight data of the second node are 1, and when the ternary memory cell stores the weight value of +1, the weight data of the first node is 2 and the inversed weight data of the second node is 0.
8 . The memory cell of claim 7 , wherein the first transistor is connected to the first node, the second transistor, and a first operation line, the second transistor is connected to the second node, the first transistor, and a second operation line, and the third transistor is connected to a third node that is a junction of the first transistor and the second transistor, and to the activation line.
9 . The memory cell of claim 8 , wherein the weight cell is configured to: receive the weight data and the inversed weight data from the ternary memory cell; receive the activation signal to activate the weight cell via the activation line; and block at least one of a first current path along the first operation line and the first transistor or a second current path along the second operation line and the second transistor, on a basis of the weight data and the inversed weight data.
10 . The memory cell of claim 8 , wherein the plurality of memory cells are connected in parallel between the first operation line and the second operation line, and a multiply and accumulate (MAC) operation is performed on a basis of a difference between a voltage applied to the first operation line and a voltage applied to the second operation line.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0084149, filed on Jun. 28, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field The disclosure relates to a memory device including a ternary memory cell, and more particularly, to a ternary weight cell circuit design method in a memory device using T-CMOS. 2. Description of the Related Art In the case of devices that process a large amount of data, such as artificial intelligence, power consumption in a data processing process is very high. To solve a power consumption problem generated in artificial intelligence, recently, ultracompact AI technology such as Internet of things (IoT) and a mobile edge end has been developed. In order to implement the ultracompact AI technology, it is required to maximize high computational efficiency with low power in a limited memory area. To maximize the computational efficiency, an AI computation accelerator that performs high-performance, high-efficiency information processing through parallel computation of large-capacity weight activation data based on a multiply and accumulate (MAC) operation is used. According to the related art, an AI computation accelerator circuit includes a weight cell array for storing weights, which are learning information, and a binary complementary metal oxide semiconductor (CMOS)-based memory cell is used to secure area efficiency and an information transmission speed. The computation method by processing such binary weight information has caused a decrease in energy efficiency due to lowering of accuracy of a computation value and an unnecessary computation operation. To improve the above problems, a technology that changes a digital method from binary to ternary recently draws attention. While a static random access memory (SRAM) cell according to a digital method according to the relates art is capable of storing information of 0 or 1, a ternary memory cell (ternary static random access memory) is capable of storing ternary information in 0, 1, 2 (or 0, 1/2, 1) in one memory cell, thereby implementing a storing capacity of 1.5 times for the same size. In contrast to the general binary logic circuit, such a ternary logic circuit can provide an advantage of processing a large amount of information, and may also be advantageous in a logic-in-memory structure that outputs a value obtained through logic operation of stored data. However, to store ternary information, a memory cell has to be designed using two memory cells, and thus, there is a problem in that the area is rather doubled or more increased. Furthermore, the methods have a problem in that a lot of standby power is consumed due to an increase in leakage current according to the improvement of a CMOS density. Recently, technology to reduce power consumption while maintaining area efficiency of a memory device has been developed. SUMMARY Provided are a ternary memory cell for calculating logic values stored in a memory cell by using a ternary logic circuit and outputting the calculated logic values, and a memory device including the same. Furthermore, provided are a device and a method for increasing an energy efficiency and area efficiency of a memory device circuit design by storing information at a low current through a T-CMOS-based ternary weight cell circuit design. Provided are a device and a method for reducing power consumption of a memory device by storing information at a low current through a T-CMOS-based ternary weight cell circuit design. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to an aspect of the disclosure, a memory cell in a memory device for a logic-in-memory includes a ternary memory cell for storing ternary data, and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line. According to another embodiment, the first transistor may be connected to the first node, the second transistor, and a first operation line, the second transistor may be connected to the second node, the first transistor, and a second operation line, and the third transistor may be connected to a third node that