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US-12619396-B2 - Random-number-generating circuit

US12619396B2US 12619396 B2US12619396 B2US 12619396B2US-12619396-B2

Abstract

A random-number-generating circuit is provided, which includes a noise-voltage generator, a voltage-controlled oscillator, a ring oscillator, and a D flip-flop (DFF). The noise-voltage generator converts an external voltage into a noise voltage. The voltage-controlled oscillator receives the noise voltage, and generates a first clock signal according to the noise voltage. The ring oscillator generates a sampling clock signal. The DFF receives the first clock signal, and samples the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

Inventors

  • Chih-Feng Lin

Assignees

  • WINBOND ELECTRONICS CORP.

Dates

Publication Date
20260505
Application Date
20220725

Claims (15)

  1. 1 . A random-number-generating circuit, comprising: a noise-voltage generator, converting an external voltage into a noise voltage; a voltage-controlled oscillator, receiving the noise voltage, and generating a first clock signal according to the noise voltage; a ring oscillator, generating a sampling clock signal; and a D flip-flop (DFF), receiving the first clock signal, and sampling the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number, wherein the noise-voltage generator comprises: a power-noise amplifier, amplifying power noise of the external voltage to generate a first voltage; a CTAT (complementary to absolute temperature) reference-voltage circuit, generating a second voltage using ambient temperature of the random-number-generating circuit; and a first operational amplifier.
  2. 2 . The random-number-generating circuit as claimed in claim 1 , wherein the first voltage is provided to a positive input terminal of the first operational amplifier through a first capacitor, and the second voltage is provided to the positive input terminal of the first operational amplifier through a first resistor.
  3. 3 . The random-number-generating circuit as claimed in claim 2 , wherein the noise voltage is input to a negative input terminal of the first operational amplifier through a feedback path.
  4. 4 . The random-number-generating circuit as claimed in claim 1 , wherein the second voltage has a negative temperature coefficient.
  5. 5 . The random-number-generating circuit as claimed in claim 1 , wherein the first voltage represents a transient level of a reference voltage, and the second voltage represents a direct-current (DC) level of the reference voltage.
  6. 6 . The random-number-generating circuit as claimed in claim 1 , wherein the second voltage determines a fundamental frequency of the first clock signal, and the first voltage temporarily changes a frequency of the first clock signal.
  7. 7 . The random-number-generating circuit as claimed in claim 1 , wherein the feedback path comprises a second resistor and a third resistor, and a first terminal and a second terminal of the second resistor are respectively connected to a second node and the negative input terminal of the first operational amplifier, and a first terminal and a second terminal of the third resistor are respectively connected to the negative input terminal of the first operational amplifier and the ground, wherein the second node is an output terminal of the first operational amplifier.
  8. 8 . The random-number-generating circuit as claimed in claim 1 , wherein the power-noise amplifier comprises a second operational amplifier, and the external voltage is connected to a third node through a second capacitor and a fourth resistor in parallel, and the third node is connected to a positive input terminal of the second operational amplifier, wherein a first terminal and a second terminal of a fifth resistor are respectively connected to the third node and the ground, and the third node is connected to a negative input terminal of the second operational amplifier through a low-pass filter formed by a sixth resistor and a third capacitor.
  9. 9 . The random-number-generating circuit as claimed in claim 1 , wherein the CTAT reference-voltage circuit comprises a seventh resistor, a diode, and a fourth capacitor, wherein a first terminal and a second terminal of the seventh resistor are respectively connected to the external voltage and a sixth node, wherein an anode and a cathode of the diode are respectively connected to the sixth node and the ground, and a first terminal and a second terminal of the fourth capacitor are respectively connected to the sixth node and the ground, wherein the sixth node is an output terminal of the CTAT reference-voltage circuit.
  10. 10 . The random-number-generating circuit as claimed in claim 1 , wherein the voltage-controlled oscillator and the ring oscillator are controlled by an enable signal, and when the enable signal is in a high-logic state, the voltage-controlled oscillator and the ring oscillator are in a working state to respectively generate the first clock signal and the sampling clock signal, wherein when the enable signal is in a low-logic state, the voltage-controlled oscillator and the ring oscillator are turned off.
  11. 11 . The random-number-generating circuit as claimed in claim 10 , wherein the ring oscillator comprises a NAND gate, a plurality of first inverters, and a second inverter that are connected in series.
  12. 12 . The random-number-generating circuit as claimed in claim 11 , wherein both the enable signal and a second clock signal generated by the last inverter among the first inverters are input to the NAND gate, and there are 2N first inverters, where N is a positive integer.
  13. 13 . The random-number-generating circuit as claimed in claim 12 , wherein the second clock signal is input to the second inverter to obtain the sampling clock signal.
  14. 14 . The random-number-generating circuit as claimed in claim 1 , wherein the first clock signal is an irregular clock signal, and the sampling clock signal is a regular clock signal.
  15. 15 . The random-number-generating circuit as claimed in claim 1 , wherein the DFF samples the first clock signal at each rising edge of the sampling clock signal to obtain the output digital signal.

Description

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to electronic circuits, and, in particular, to a random-number-generating circuit. Description of the Related Art Random number generators (RNGs) play an important role in many different applications, such as cryptographic applications, statistical computing, the row-hammer mechanism in dynamic random access memories (DRAMs), and more. However, conventional random number generators have related circuits, such as linear feedback displacement registers and ring-oscillator-based random-number generators. As a result, the numbers that are generated are often not real random numbers, but are certain deterministic/periodic pseudo-random numbers. BRIEF SUMMARY OF THE INVENTION In view of the above, a random-number-generating circuit is provided in the present invention to solve the aforementioned problem. An embodiment of the present invention provides a random-number-generating circuit is provided, which includes a noise-voltage generator, a voltage-controlled oscillator, a ring oscillator, and a D flip-flop (DFF). The noise-voltage generator converts an external voltage into a noise voltage. The voltage-controlled oscillator receives the noise voltage, and generates a first clock signal according to the noise voltage. The ring oscillator generates a sampling clock signal. The DFF receives the first clock signal, and samples the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number. BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: FIG. 1 is a block diagram of a random-number-generating circuit in accordance with an embodiment of the invention; FIG. 2 is a schematic diagram of the power-noise amplifier and the CTAT reference-voltage circuit in accordance with an embodiment of the invention; FIG. 3A is a diagram showing the relationship between the voltage VT and temperature in accordance with an embodiment of the invention; FIG. 3B is a diagram showing the voltages VT and VP in accordance with an embodiment of the invention; FIG. 3C is a diagram showing the reference VMIX in accordance with an embodiment of the invention; FIG. 4 is a diagram of the ring oscillator in accordance with an embodiment of the invention; and FIG. 5 is a waveform diagram of the sampling operations of the D flip-flop in accordance with the embodiment of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION The following description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The scope of the disclosure is best determined by reference to the appended claims. It should be understood that the words “comprising”, “including” and the like used in this specification are used to indicate the existence of specific technical characteristics, numerical values, method steps, work processes, components and/or components, but not It does not exclude that you can add more technical features, values, method steps, job processing, components, components, or any combination of the above. The terms such as “first”, “second”, and “third” are used in the claims to modify the elements in the claims, and are not used to indicate that there is a priority order, prior relationship, or is a component before another component, or the time sequence when performing method steps, only used to distinguish components with the same name. FIG. 1 is a block diagram of a random-number-generating circuit in accordance with an embodiment of the invention. As shown in FIG. 1, the random-number-generating circuit 100 may include a noise-voltage generator 110, a voltage-controlled oscillator 120, a ring oscillator 130, and a D flip-flop (DFF) 140. The noise-voltage generator 110 may be used to convert an external voltage VEXT into a noise voltage V1, and provide the noise voltage V1 to the voltage-controlled oscillator 120. The voltage-controlled oscillator 120 may generate an irregular clock signal f1 according to the noise voltage V1. The ring oscillator 130 may be used for generating a sampling clock signal f2, wherein the sampling clock signal f2 is a regular clock signal. In addition, the sampling clock signal f2 is provided to an clock-input terminal CLK of the DFF 140 to sample the clock signal f1 input into the data terminal D of the DFF 140 to generate an output digital signal fmix at the output terminal Q of the DFF 140, wherein the output digital signal fmix represents a random number. The noise-voltage generator 110 may include a power-noise amplifier 112, a CTAT (complementary to absolute temperature) reference-voltage circuit 114, and an operational amplifier 116. The power-noise amplifier 112 may be used for amplify the power noise of the external voltage VEXT to gen