US-12619436-B2 - Apparatus and operation method for distributed processing of plural operations in data storage system

US12619436B2US 12619436 B2US12619436 B2US 12619436B2US-12619436-B2

Abstract

A data storage system includes a controller comprising pipelined multiple processors. The controller is configured to: generate plural instructions having dependency based on a command, input from an external device, for controlling at least one storage device to perform an operation corresponding to the command; allocate the plural instructions to the pipelined multiple processors in stages; and reallocate, when a number of second instructions allocated to a second processor of the pipelined multiple processors becomes a first threshold or greater, at least one of the second instructions to a first processor of the multiple processors.

Inventors

Ku Ik KWON
Byoung Min JIN
Gyu Yeul HONG

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260505
Application Date: 20231121
Priority Date: 20230630

Claims (20)

1 . A data storage system comprising a controller comprising pipelined multiple processors, wherein the controller is configured to: generate plural instructions based on one of a read command, a write command, and an erase command, input from an external device, wherein the plural instructions are for controlling a data input/output operation performed within at least one storage device and at least one instruction among the plural instructions has dependency on one or more other instructions among the plural instructions; allocate the plural instructions to the pipelined multiple processors in stages, wherein the dependency requires for allocation of the plural instructions that the one or more other instructions are executed at an earlier stage than the at least one instruction executed at a later stage; and reallocate, when a number of second instructions allocated to a second processor of the pipelined multiple processors becomes a first threshold or greater, at least one of the second instructions to a first processor of the multiple processors, wherein the controller determines based on the dependency a correct order of processing of the plural instructions to avoid bottlenecks in the processing.
2 . The data storage system according to claim 1 , wherein the pipelined multiple processors comprises N number of processors, where N is equal to or greater than 2, and wherein the N number of processors are individually configured to carry out one or more instructions, allocated thereto, among the plural instructions according to N number of stages having the dependency.
3 . The data storage system according to claim 2 , wherein the controller further comprises a task monitoring circuitry configured to: check N number of queues each configured to enqueue therein one or more instructions allocated to a corresponding processor of the N number of processors, and determine an operating state of each of the N number of processors based on a result of the checking.
4 . The data storage system according to claim 3 , wherein the task monitoring circuitry determines the operating state based on an instruction level of the corresponding processor as one of: high when a number of the instructions allocated to the corresponding processor is the first threshold or greater, medium when the number of the instructions allocated to the corresponding processor is a second threshold or greater and less than the first threshold, and low when the number of the instructions allocated to the corresponding processor is less than the second threshold.
5 . The data storage system according to claim 4 , wherein the second processor corresponds to a subsequent stage to a preceding stage corresponding to the first processor among the N number of stages, and wherein the task monitoring circuitry is configured to reallocate the at least one of second instructions, which have been allocated to the second processor, to the first processor when the instruction level of the first processor is low.
6 . The data storage system according to claim 5 , wherein the task monitoring circuitry is configured to preferentially select a second instruction among the second instructions allocated to the second processor, when the selected second instruction has the dependency to one of the first instructions enqueued in a first queue corresponding to the first processor among the N number of queues but no instructions has the dependency to the selected second instruction.
7 . The data storage system according to claim 6 , wherein the selected second instruction is an earliest second instruction to be carried out among the second instructions.
8 . The data storage system according to claim 5 , wherein the task monitoring circuitry is further configured to, after reallocating the at least one of second instructions, reallocate a third instruction from a third processor to the second processor, the third instruction having the dependency to the at least one of second instructions.
9 . The data storage system according to claim 1 , wherein the controller allocates the plural instructions by: determining, based on maximum numbers of instructions that can be carried out by the respective multiple processors, each size of queues each configured to enqueue therein one or more instructions allocated to a corresponding processor of the pipelined multiple processors; and allocating the plural instructions to the pipelined multiple processors based on the determined size.
10 . The data storage system according to claim 1 , wherein the first processor has a higher stage than the second processor, and wherein the controller is configured to, for the reallocating, preferentially select the at least one of second instructions, a number of which is less than a difference between the first threshold and a second threshold lower than the first threshold.
11 . The data storage system according to claim 1 , wherein the controller is further configured to carry out tasks of the plural instructions based on an allocated sequence at each of the pipelined multiple processors and the dependency between the plural instructions.
12 . A method for operating a data storage system, the method comprising: receiving one of a read command, a write command, and an erase command input from a host; generating plural instructions according to the command, wherein the plural instructions are for controlling a data input/output operation performed within at least one storage device and at least one instruction among the plural instructions has dependency on one or more other instructions among the plural instructions; allocating the plural instructions to pipelined multiple processors in stages, wherein the dependency requires for allocation of the plural instructions that the one or more other instructions are executed at an earlier stage than the at least one instruction executed at a later stage; reallocating, when a number of second instructions allocated to a second processor of the multiple processors becomes a first threshold or greater, at least one of the second instructions to a first processor of the multiple processors; and carrying out tasks of the plural instructions based on an allocated sequence at each of the pipelined multiple processors and the dependency between the plural instructions, wherein a correct order of processing of the plural instructions based on the dependency avoids bottlenecks in the processing.
13 . The method according to claim 12 , wherein the pipelined multiple processors comprise N number of processors, where N is equal to or greater than 2, and wherein the carrying out the plural instructions comprises carrying out, through each of the processors, one or more instructions that are allocated to the processor among the plural instructions according to N number of stages having the dependency.
14 . The method according to claim 13 , wherein the reallocating the at least one instruction comprises: checking N number of queues each configured to enqueue therein one or more instructions allocated to a corresponding processor of the N number of processors; and determining an operating state of each of the N number of processors based on a result of the checking.
15 . The method according to claim 14 , wherein the determining the operating state comprises determining an instruction level of the corresponding processor as one of: high when a number of the instructions allocated to the corresponding processor is the first threshold or greater, medium when the number of the instructions allocated to the corresponding processor is a second threshold or greater and less than the first threshold, and low when the number of the instructions allocated to the corresponding processor is less than the second threshold.
16 . The method according to claim 15 , wherein the second processor corresponds to a subsequent stage to a preceding stage corresponding to the first processor among the N number of stages, and wherein the at least one of second instructions, which have been allocated to the second processor, is reallocated to the first processor when the instruction level of the first processor is low, until the instruction level of the first processor becomes medium after the reallocating.
17 . The method according to claim 16 , wherein the at least one of second instructions is preferentially selected among the second instructions allocated to the second processor, when the selected second instruction has the dependency to one of the first instructions enqueued in a first queue corresponding to the first processor among the N number of queues but no instructions have the dependency to the selected second instruction.
18 . The method according to claim 17 , wherein the selected second instruction is an earliest second instruction to be carried out among the second instructions.
19 . The method according to claim 16 , further comprising reallocating, to the second processor, a third instruction having the dependency to the selected second instruction, after the reallocating of the at least one of second instructions.
20 . The method according to claim 12 , wherein the allocating the at least one of the second instructions includes: determining, based on maximum numbers of instructions that can be carried out by the respective multiple processors, each size of queues each configured to enqueue therein one or more instructions allocated to a corresponding processor of the multiple processors; and allocating the plural instructions to the multiple processors based on the determined size.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims the benefit of priority under 35 U.S.C. § 119 (a) to Korean Patent Application No. 10-2023-0085273, filed on Jun. 30, 2023, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD One or more embodiments of the present disclosure described herein relate to a data storage system, and more particularly, to an apparatus and a method for distributed processing to improve data input/output performance in the data storage system. BACKGROUND A memory device or a memory system is typically used as an internal circuit, a semiconductor circuit, an integrated circuit, and/or a removable device in a computing system or an electronic apparatus. There are various types of memory, including a volatile memory and a non-volatile memory. The volatile memory may require power to maintain data. The volatile memory may include a random access memory (RAM), a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), and the like. The non-volatile memory can maintain data stored therein when power is not supplied. The non-volatile memory may include a NAND flash memory, a NOR flash memory, a Phase Change Random Access Memory (PCRAM), a Resistant Random Access Memory (RRAM), a Magnetic Random Access Memory (MRAM), etc. BRIEF DESCRIPTION OF THE DRAWINGS The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the figures. FIG. 1 illustrates a data storage system according to an embodiment of the present disclosure. FIG. 2 illustrates allocation of instructions to multiple processors having a pipelined structure according to an embodiment of the present disclosure. FIG. 3 illustrates reallocation of instructions according to an embodiment of the present disclosure. FIG. 4 illustrates allocation of instructions according to another embodiment of the present disclosure. FIG. 5 illustrates reallocation of instructions according to another embodiment of the present disclosure. FIG. 6 illustrates a data processing system according to an embodiment of the present disclosure. FIG. 7 illustrates a data storage system according to an embodiment of the present disclosure. FIG. 8 illustrates a method for operating a data storage system according to an embodiment of the present disclosure. FIG. 9 illustrates an effect of reallocation according to an embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments of the present disclosure are described below with reference to the accompanying drawings. Elements and features of this disclosure, however, may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments. In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiment,” and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments. In this disclosure, the terms “comprise,” “comprising,” “include,” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. The terms in a claim do not foreclose the apparatus from including additional components e.g., an interface unit, circuitry, etc. In this disclosure, various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the blocks/units/circuits/components include structure (e.g., circuitry) that performs one or more tasks during operation. As such, the block/unit/circuit/component can be said to be configured to perform the task even when the specified block/unit/circuit/component is not currently operational, e.g., is not turned on nor activated. Examples of block/unit/circuit/component used with the “configured to” language include hardware, circuits, memory storing program instructions executable to implement the operation, etc. Additionally, “configured to” can include a generic structure, e.g., generic circuitry, that is manipulated by software and/or firmware, e.g., an FPGA or a general-purpose processor executing software to operate in a manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process, e.g., a semiconductor fabrication facility, to fabricate devices, e.g., integrated circuits that are adapted to implement or perform one or more tasks. As used i