US-12619457-B2 - Merging data for write allocate

Abstract

A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

Inventors

• Abhijeet Ashok Chachad
• David Matthew Thompson

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260505

Application Date

20230919

Claims (20)

1. 1 . A device comprising: a cache memory; a write buffer that includes an entry; and a cache controller coupled to the cache memory and to the write buffer and configured to: receive a write request to write a first set of data to an address; store the first set of data in the entry of the write buffer; receive a second set of data that is read from the address; merge the first set of data and the second set of data to produce a merged set of data; store the merged set of data in the entry of the write buffer; and cause the merged set of data to be stored in the cache memory.
2. 2 . The device of claim 1 , wherein: the entry includes a data field and an enable field; and the cache controller is configured to store a set of values in the enable field that specifies a subset of the data field that stores the first set of data.
3. 3 . The device of claim 2 , wherein the cache controller is configured to store a set of zero values in the enable field based on the merged set of data being stored in the data field.
4. 4 . The device of claim 2 , wherein: the data field is configured to store a set of bytes; and the enable field is configured to store a respective bit for each byte of the set of bytes of the data field.
5. 5 . The device of claim 1 , wherein the write buffer is a first-in-first-out (FIFO) buffer.
6. 6 . The device of claim 5 , further comprising: a FIFO address buffer and a FIFO enable buffer coupled to the cache controller.
7. 7 . The device of claim 1 further comprising: a first cache system that includes the cache memory, the write buffer, and the cache controller; and a second cache system, wherein the cache controller is coupled to the second cache system and is configured to retrieve the second set of data from the second cache system.
8. 8 . The device of claim 7 , wherein: the first cache system is a level two (L2) cache system; and the second cache system is a level three (L3) cache system.
9. 9 . The device of claim 1 , wherein the write request specifies the first set of data.
10. 10 . The device of claim 1 , wherein the first set of data includes a set of discontiguous bytes of data.
11. 11 . A device comprising: a processor configured to provide a write allocate request that specifies a first set of data to be written to an address; a cache system coupled to the processor, wherein the cache system includes: a cache memory; a write buffer that includes an entry; and a cache controller coupled to the cache memory and to the write buffer and configured to, based on the write allocate request: store the first set of data in the entry of the write buffer; receive a second set of data that is read from the address; merge the first set of data and the second set of data to produce a merged set of data; store the merged set of data in the entry; and cause the merged set of data to be stored in the cache memory.
12. 12 . The device of claim 11 , wherein: the entry includes a data field and an enable field; and the cache controller is configured to store a set of values in the enable field that specifies a subset of the data field that stores the first set of data.
13. 13 . The device of claim 12 , wherein the cache controller is configured to store a set of zero values in the enable field based on the merged set of data being stored in the data field.
14. 14 . The device of claim 12 , wherein: the data field is configured to store a set of bytes; and the enable field is configured to store a respective bit for each byte of the set of bytes of the data field.
15. 15 . The device of claim 14 , wherein: the cache system is a first cache system; the device further comprises a second cache system; and the cache controller is coupled to the second cache system and is configured to retrieve the second set of data from the second cache system.
16. 16 . A method comprising: receiving, by a cache controller, a write request to write a first set of data to an address; causing, by the cache controller, the first set of data to be stored in an entry of a write buffer; receiving a second set of data that is read from the address; merging, by the cache controller, the first set of data and the second set of data to produce a merged set of data; causing, by the cache controller, the merged set of data to be stored in the entry of the write buffer; and causing, by the cache controller, the merged set of data to be stored in a cache memory.
17. 17 . The method of claim 16 , wherein: the entry includes a data field and an enable field; and the method comprises causing, by the cache controller, a set of values to be stored in the enable field that specifies a subset of the data field that stores the first set of data.
18. 18 . The method of claim 17 further comprising causing, by the cache controller, a set of zero values to be stored in the enable field based on the merged set of data being stored in the entry of the write buffer.
19. 19 . The method of claim 16 , wherein: the cache memory, the write buffer, and the cache controller are associated with a first cache system; and the method further comprises retrieving, by the cache controller, the second set of data from a second cache system.
20. 20 . The method of claim 19 , wherein: the first cache system is a level two (L2) cache system; and the second cache system is a level three (L3) cache system.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. patent application Ser. No. 17/542,573, filed on Dec. 6, 2021, which is a continuation of U.S. patent application Ser. No. 16/882,356, filed on May 22, 2020, now U.S. Pat. No. 11,194,617, which claims priority to U.S. Provisional Patent Application No. 62/852,461, filed on May 24, 2019, each of which is hereby incorporated herein by reference in its entirety. BACKGROUND Some memory systems include a multi-level cache system, in which a hierarchy of memories (e.g., caches) provides varying access speeds to cache data. A first level (L1) cache is closely coupled to a central processing unit (CPU) core and provides the CPU core with faster access (e.g., relative to main memory) to cache data. A second level (L2) cache is also coupled to the CPU core and, in some examples, is larger and thus holds more data than the L1 cache, although the L2 cache provides relatively slower access to cache data than the L1 cache. Additional memory levels of the hierarchy are possible. SUMMARY In accordance with at least one example of the disclosure, a method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request. In accordance with another example of the disclosure, a method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, creating a masked subset of ways in the set by masking any way having a cache coherence state indicating that another request is pending for the way, randomly selecting one of the ways in the masked subset, and allocating the selected way for the first request. In accordance with yet another example of the disclosure, a level two (L2) cache subsystem includes a L2 cache configured as an N-way set associative cache and a L2 controller configured to receive a first request to allocate a line in the L2 cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocate the way for the first request. The L2 controller is also configured to, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly select one of the ways in the set. The L2 controller is also configured to, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocate the selected way for the first request. In accordance with at least one example of the disclosure, a method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in the pipeline; determining whether the first transaction comprises a high priority transaction or a low priority transaction; in response to the first transaction comprising a high priority transaction, processing the high priority transaction by sending the high priority transaction to an output buffer; receiving a second transaction from the previous stage; and determining whether the second transaction comprises a high priority transaction or a low priority transaction. In response to the second transaction comprising a low priority transaction, the method includes processing the low priority transaction by monitoring a full signal from the output buffer while sending the low priority transaction to the output buffer; in response to the full signal being asserted and no high priority transaction being available from the previous stage, pausing processing of the low priority transaction; in response to the full signal being asserted and a high priority transaction being available from the previous stage, stopping processing of the low priority transaction and processing the high priority transaction; and in response to the full signal being de-asserted, processing the low priority transaction by sending the low priority transaction to the output buffer. In accordance with another example of the disclosure, a method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in a pipeline; determining whether the first transaction compri