US-12619468-B2 - Hardware integrated, priority-encoded domains

US12619468B2US 12619468 B2US12619468 B2US 12619468B2US-12619468-B2

Abstract

Systems and methods for priority encoded domains in an SoC have been described. In an illustrative, non-limiting embodiment, a processing system in an SoC, may include: a core, and a domain access controller coupled to the core. The domain access controller may be configured to: receive a resource transaction request from a master device associated with a software-defined processing domain, and process the resource transaction request based upon a priority level of the software-defined processing domain. The domain access controller may also order a plurality of resource transaction requests based upon the associated respective priority levels, and provide the resource transaction requests to resources based on the order. A hypervisor can also use the priority levels of the software-defined processing domains to allocate a plurality of virtual machines to a plurality of processing cores according to the priority levels.

Inventors

Gareth Owen Shelley
David McDaid
Steven Bruce McAslan

Assignees

NXP USA, INC.

Dates

Publication Date: 20260505
Application Date: 20221216

Claims (18)

1 . A System-on-Chip (SoC), comprising: a core; a domain access controller coupled to the core, wherein the domain access controller is configured to: receive a resource transaction request from a master device associated with a software-defined processing domain; and process the resource transaction request, at least in part, based upon a priority level of the software-defined processing domain; a plurality of software-defined processing domains, wherein each of the plurality of software-defined processing domains is associated with a respective domain identifier and a respective priority level, and wherein the resource transaction request comprises a domain identifier associated with the software-defined processing domain; a plurality of cores and a hypervisor, wherein the plurality of software-defined processing domains comprise a plurality of virtual machines, and wherein the hypervisor is configured to allocate the plurality of virtual machines to the plurality of cores according to a corresponding priority level of each respective virtual machine, wherein the hypervisor is further configured to: determine that a first virtual machine of the plurality of virtual machines awaits access to one of the plurality of cores; determine that a first priority level associated with the first virtual machine is greater than a second priority level associated with a second virtual machine of the plurality of virtual machines currently allocated to a first core of the plurality of cores; deallocate, from the first core, the second virtual machine whose associated second priority level is less than the first priority level associated with the first virtual machine; and allocate the first virtual machine to the first core.
2 . The SoC of claim 1 , wherein the domain access controller is further configured to determine, for the resource transaction request, at least one of: that the domain identifier of the resource transaction request matches a domain identifier of a resource to which the resource transaction request is addressed; or that access rights of one of the software-defined processing domain matches access rights of the resource.
3 . The SoC of claim 1 , wherein the domain access controller is further configured to: receive a plurality of resource transaction requests, including the resource transaction request, associated with a plurality of software-defined processing domains, including the software-defined processing domain, and addressed to a resource coupled to the domain access controller, wherein each software-defined processing domain is associated with a respective priority level; and wherein to process the resource transaction request, at least in part, based upon the priority level of the software-defined processing domain, the domain access controller is further configured to: order the plurality of resource transaction requests based upon the associated respective priority levels; and provide the resource transaction requests to the resource based on the order.
4 . The SoC of claim 3 , wherein the resource comprises a memory resource or a remote peripheral resource, and wherein the resource transaction requests comprise memory transactions or access requests for the remote peripheral.
5 . The SoC of claim 1 , further comprising a plurality of resources, wherein a distinct domain access controller is coupled to each of the plurality of resources.
6 . The SoC of claim 1 , further comprising a plurality of resources, wherein each domain identifier for each of the plurality of software-defined processing domains is associated with one or more of the resources.
7 . The SoC of claim 1 , wherein the master device comprises a memory configured to store the respective domain identifier and the respective priority level for each of the plurality of software-defined processing domains.
8 . The SoC of claim 1 , further comprising a plurality of cores, wherein at least two of the plurality of cores are configured to execute different operating systems.
9 . A System-on-Chip (SoC), comprising: a core; a domain access controller coupled to the core, wherein the domain access controller is configured to: receive a resource transaction request from a master device associated with a software-defined processing domain; and process the resource transaction request, at least in part, based upon a priority level of the software-defined processing domain; a plurality of software-defined processing domains, wherein each of the plurality of software-defined processing domains is associated with a respective domain identifier and a respective priority level, and wherein the resource transaction request comprises a domain identifier associated with the software-defined processing domain; and a plurality of cores and an operating system, wherein the plurality of software-defined processing domains comprise a plurality of applications managed by the operating system, and wherein the operating system is configured to allocate the plurality of applications to the plurality of cores according to a corresponding priority level of each of the applications, wherein the operating system is further configured to: determine that a first application of the plurality of applications awaits access to one of the plurality of cores; determine that a first priority level associated with the first application is greater than a second priority level associated with a second application of the plurality of applications currently allocated to a first core the plurality of cores; deallocate, from the first core, the second application whose associated second priority level is less than the first priority level associated with the first application; and allocate the first application to the first core.
10 . The SoC of claim 9 , wherein the domain access controller is further configured to determine, for the resource transaction request, at least one of: that the domain identifier of the resource transaction request matches a domain identifier of a resource to which the resource transaction request is addressed; or that access rights of one of the software-defined processing domain matches access rights of the resource.
11 . The SoC of claim 9 , wherein the domain access controller is further configured to: receive a plurality of resource transaction requests, including the resource transaction request, associated with a plurality of software-defined processing domains, including the software-defined processing domain, and addressed to a resource coupled to the domain access controller, wherein each software-defined processing domain is associated with a respective priority level; and wherein to process the resource transaction request, at least in part, based upon the priority level of the software-defined processing domain, the domain access controller is further configured to: order the plurality of resource transaction requests based upon the associated respective priority levels; and provide the resource transaction requests to the resource based on the order.
12 . The SoC of claim 11 , wherein the resource comprises a memory resource or a remote peripheral resource, and wherein the resource transaction requests comprise memory transactions or access requests for the remote peripheral.
13 . The SoC of claim 9 , further comprising a plurality of resources, wherein a distinct domain access controller is coupled to each of the plurality of resources.
14 . The SoC of claim 9 , further comprising a plurality of resources, wherein each domain identifier for each of the plurality of software-defined processing domains is associated with one or more of the resources.
15 . The SoC of claim 9 , wherein the master device comprises a memory configured to store the respective domain identifier and the respective priority level for each of the plurality of software-defined processing domains.
16 . The SoC of claim 9 , further comprising a plurality of cores, wherein at least two of the plurality of cores are configured to execute different operating systems.
17 . A system, comprising: a plurality of processing cores; a memory coupled to at least one of the plurality of processing cores, wherein the memory has program instructions stored thereon that, upon execution by one or more of the processing cores, cause the system to execute a hypervisor to: access domain information in a master device, the domain information comprising a plurality of domain identifiers and a plurality of priority levels, each of the domain identifiers and priority levels associated with a respective one of a plurality of virtual machines; and allocate each of the plurality of virtual machines to a respective one of the plurality of processing cores according to the priority levels; a domain access controller coupled to an interconnect; and a plurality of resources connected to the domain access controller via the interconnect, wherein: (a) the hypervisor is configured to provide the domain identifiers to the domain access controller, wherein the domain access controller is coupled to the interconnect between the hypervisor and the plurality of resources; and (b) the domain access controller comprises at least one message queue for one or more of the plurality of resources, wherein the domain access controller is configured to: determine whether domain identifiers in messages from the virtual machines match domain identifiers of any of the one or more resources; and allow the messages to pass to the at least one message queue in response to the domain identifiers matching domain identifiers of any of the one or more resources.
18 . The system of claim 17 , wherein the domain access controller is further configured to: determine a priority level associated with each of the allowed messages; determine an order for the allowed messages according to associated priority levels; and provide the allowed messages to the resource in the determined order.

Description

FIELD The present disclosure relates generally to computer architectures and, more particularly, to virtualization and priority of resources in a processing device. BACKGROUND In a data processing system, various resources, such as bus masters, memory devices, and peripherals, can be grouped into common domains. Each group can be referred to as a resource domain and can include one or more data processors, memory devices, and peripheral devices. Applications are executed by a processor whose execution is controlled by an operating system. The operating system interfaces directly with the hardware components of the processor and the hardware components coupled to the processor. In this configuration, if another operating system, such as another instance of an operating system, is needed, another processor and hardware components would be added to the configuration. In an attempt to reduce the costs, particularly hardware costs, some systems employ virtualization techniques by sharing the hardware with multiple instances of an operating system, or different operating systems. In one such system, a host operating system runs multiple instances of child operating systems or two or more different operating systems. Virtualization is performed by a host process, referred to as a hypervisor, that allows multiple instances of child operating systems to share a single processor and virtualized hardware resources. The hypervisor enables general freedom of interference: i.e. application X cannot influence application Y. and may also isolate the applications from one another, such that a failure in one application does not cause a failure in the other applications or the hardware platform. BRIEF DESCRIPTION OF THE DRAWINGS The present invention(s) are illustrated by way of example and are not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 illustrates a block diagram of a processing system in accordance with selected embodiments of the invention. FIG. 2 illustrates a block diagram of an extended Resource Domain Controller (“XRDC”) within a processing system, according to some embodiments. FIG. 3 illustrates further details of the operation of the XRDC within the processing system, according to some embodiments. FIGS. 4A and 4B illustrates a block diagram of some components in an SoC, with some of the components grouped into two domains, according to some embodiments. FIG. 5 illustrates a register configuration for the implementation of a Master Domain Priority Level (“MDPL”) and a Sub Domain Priority Level (“SDPL”) within an XRDC system. FIGS. 6A & 6B illustrate a specific example of an MDPL and SDPL register configuration, and how that register configuration translates into Domain Priority Levels for domains in an XRDC system, according to some embodiments. FIG. 7A illustrates a memory transaction reordering example of an XRDC system without use of the MDPL and SDPL registers, according to some embodiments. FIG. 7B illustrates a memory transaction reordering example of an XRDC system, using the MDPL and SDPL registers for transaction queue reordering, according to some embodiments. FIGS. 8A, 8B, and 8C illustrate context switch policing examples for potentially swapping higher priority tasks for current active tasks at processing cores, according to some embodiments. DETAILED DESCRIPTION Some embodiments of the hardware integrated priority encoded domains provide an extension for extended Resource Domain Controller (“XRDC”). The XRDC is a configurable module that allows the creation of software defined processing domains, that are enforced by hardware on a device. In some embodiments disclosed herein, the domains are used by a multi-core master device to provide partitioning and protection configuration across an interface. The domain identifiers can be used by software components, such as virtual machines or applications, in the master device. These domain identifiers can also be provided to a domain access controller for access to other components on an SoC, such as memory, as well as peripherals. The domain access controller interprets the incoming messages and allows access to the corresponding internal or external components by messages that match the domain identifier and access permissions of the corresponding component. In some embodiments, an overall controlling component, such as a hypervisor or operating system, can have the highest privilege of all hardware or software being executed by the master device. During startup or reboot, the overall controlling component is activated, before any other functions, to read domain configuration files that identify the internal or external resources, including peripheral devices, included in each domain. The domain information is provided to other lower privilege components (such as virtual machines in the cas