US-12619480-B2 - Application programming interface to indicate event dependencies

Abstract

Apparatuses, systems, and techniques to perform an application programming interface (API) to add one or more graph nodes to a software graph, wherein the API is to store an indication of whether a node within a software graph was performed based, at least in part, on a dependency type indicated by the API. In at least one embodiment, one or more nodes are added to a graph in accordance to one or more dependency types.

Inventors

• David Anthony Fontaine
• Steven Arthur Gurfinkel

Assignees

• NVIDIA CORPORATION

Dates

Publication Date

20260505

Application Date

20230227

Claims (20)

1. 1 . One or more processors, comprising: circuitry to, in response to an application programming interface (API) call, store an indication of whether a node within a software graph was performed based, at least in part, on a dependency type indicated by the API call.
2. 2 . The one or more processors of claim 1 , wherein the circuitry is to store the indication of whether the node within the software graph was performed, based, at least in part, on one or more edges of the software graph, the one or more edges terminating to or originating from the node.
3. 3 . The one or more processors of claim 1 , wherein the API call is to further indicate a port identifier of a graph node associated with the node.
4. 4 . The one or more processors of claim 1 , wherein the circuitry is to store the indication of whether the node within the software graph was performed by identifying one or more graph nodes of the software graph dependent to or dependent on the node.
5. 5 . The one or more processors of claim 1 , wherein the dependency type includes one or more of a full execution dependency, a launch order dependency, or an anti-deadlock dependency.
6. 6 . The one or more processors of claim 1 , wherein the node is to be performed by one or more graphics processing units (GPUs) based, at least in part, on the dependency type.
7. 7 . The one or more processors of claim 1 , wherein the API call is to receive a set of parameters comprising an identifier of the node and dependency information corresponding to the dependency type.
8. 8 . A computer-implemented method comprising: receiving an application programming interface (API) call; and in receipt of the API call, storing an indication of whether a node within a software graph was performed based, at least in part, on a dependency type indicated by the API call.
9. 9 . The computer-implemented method of claim 8 , further comprising, storing the indication of whether the node within the software graph was performed, based, at least in part, on one or more edges of the software graph, the one or more edges terminating to or originating from the node.
10. 10 . The computer-implemented method of claim 8 , wherein the API call is to further indicate a port identifier of a graph node associated with the node.
11. 11 . The computer-implemented method of claim 8 , further comprising, storing the indication of whether the node within the software graph was performed by identifying one or more graph nodes of the software graph dependent to or dependent on the node.
12. 12 . The computer-implemented method of claim 8 , wherein the dependency type includes one or more of a full execution dependency, a launch order dependency, or an anti-deadlock dependency.
13. 13 . The computer-implemented method of claim 8 , wherein the node is to be performed by one or more graphics processing units (GPUs) based, at least in part, on the dependency type.
14. 14 . The computer-implemented method of claim 8 , wherein the API call is to receive a set of parameters comprising an identifier of the node and dependency information corresponding to the dependency type.
15. 15 . A computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, are to cause the one or more processors to, in response to an application programming interface (API) call, store an indication of whether a node within a software graph was performed based, at least in part, on a dependency type indicated by the API call.
16. 16 . The computer system of claim 15 , wherein the is one or more processors are to store the indication of whether the node within the software graph was performed, based, at least in part, on one or more edges of the software graph, the one or more edges terminating to or originating from the node.
17. 17 . The computer system of claim 15 , wherein the API call is to further indicate a port identifier of a graph node associated with the node.
18. 18 . The computer system of claim 15 , wherein the is one or more processors are to store the indication of whether the node within the software graph was performed by identifying one or more graph nodes of the software graph dependent to or dependent on the node.
19. 19 . The computer system of claim 15 , wherein the dependency type includes one or more of a full execution dependency, a launch order dependency, or an anti-deadlock dependency.
20. 20 . The computer system of claim 15 , wherein the API call is to receive a set of parameters comprising an identifier of the node and dependency information corresponding to the dependency type.

Description

FIELD At least one embodiment pertains to techniques for parallel computing. For example, at least one embodiment pertains to processors or computing systems used to perform an application programming interface (API) to store an indication of whether a node within a software graph was performed based, at least in part, on a dependency type indicated by the API. BACKGROUND Parallel computing programs, when scheduling tasks, may cause one or more tasks of a software graph to depend from one or more other tasks. Tasks are performed according to a category of dependency between tasks. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates graph creation and execution, in accordance with at least one embodiment; FIG. 2 illustrates an illustrates an example of graph creation, in accordance with at least one embodiment; FIG. 3 is an example diagram illustrating node dependencies, in accordance with at least one embodiment; FIG. 4 is an example diagram illustrating dependency edge information, in accordance with at least one embodiment; FIG. 5 is an example diagram illustrating edge information, in accordance with at least one embodiment; FIG. 6 is a block diagram illustrating a child graph node operation, in accordance with at least one embodiment; FIG. 7 is a block diagram illustrating an empty graph node operation, in accordance with at least one embodiment; FIG. 8 is a block diagram illustrating an event record node operation, in accordance with at least one embodiment; FIG. 9 is a block diagram illustrating an event wait node operation, in accordance with at least one embodiment; FIG. 10 is a block diagram illustrating an external semaphore signal node operation, in accordance with at least one embodiment; FIG. 11 is a block diagram illustrating an external semaphore wait node operation, in accordance with at least one embodiment; FIG. 12 is a block diagram illustrating a host node operation, in accordance with at least one embodiment; FIG. 13 is a block diagram illustrating a kernel node operation, in accordance with at least one embodiment; FIG. 14 is a block diagram illustrating a memory allocation operation, in accordance with at least one embodiment; FIG. 15 is a block diagram illustrating a memory allocation operation, in accordance with at least one embodiment; FIG. 16 is a block diagram illustrating a memory copy operation, in accordance with at least one embodiment; FIG. 17 is a block diagram illustrating a one dimensional (“1D”) memory copy operation, in accordance with at least one embodiment; FIG. 18 is a block diagram illustrating a memory copy from symbol operation, in accordance with at least one embodiment; FIG. 19 is a block diagram illustrating a memory copy to symbol operation, in accordance with at least one embodiment; FIG. 20 is a block diagram illustrating a memory set operation, in accordance with at least one embodiment; FIG. 21 is a block diagram illustrating an add dependency operation, in accordance with at least one embodiment; FIG. 22 is a block diagram illustrating a remove dependency operation, in accordance with at least one embodiment; FIG. 23 is a block diagram illustrating a get node operation, in accordance with at least one embodiment; FIG. 24 is a block diagram illustrating a get edge operation, in accordance with at least one embodiment; FIG. 25 is a block diagram illustrating a get dependency operation, in accordance with at least one embodiment; FIG. 26 is a block diagram illustrating an update dependency operation, in accordance with at least one embodiment; FIG. 27 illustrates an example of a processor, according to at least one embodiment; FIG. 28 illustrates an exemplary data center, in accordance with at least one embodiment; FIG. 29 illustrates a processing system, in accordance with at least one embodiment; FIG. 30 illustrates a computer system, in accordance with at least one embodiment; FIG. 31 illustrates a system, in accordance with at least one embodiment; FIG. 32 illustrates an exemplary integrated circuit, in accordance with at least one embodiment; FIG. 33 illustrates a computing system, according to at least one embodiment; FIG. 34 illustrates an APU, in accordance with at least one embodiment; FIG. 35 illustrates a CPU, in accordance with at least one embodiment; FIG. 36 illustrates an exemplary accelerator integration slice, in accordance with at least one embodiment; FIGS. 37A and 37B illustrate exemplary graphics processors, in accordance with at least one embodiment; FIG. 38A illustrates a graphics core, in accordance with at least one embodiment; FIG. 38B illustrates a GPGPU, in accordance with at least one embodiment; FIG. 39A illustrates a parallel processor, in accordance with at least one embodiment; FIG. 39B illustrates a processing cluster, in accordance with at least one embodiment; FIG. 39C illustrates a graphics multiprocessor, in accordance with at least one embodiment; FIG. 40 illustrates a graphics processor, in accordance with at least