US-12619493-B2 - Flexible bit quantities for error correction code (ECC) values in a memory environment

US12619493B2US 12619493 B2US12619493 B2US 12619493B2US-12619493-B2

Abstract

Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.

Inventors

Keun Soo Song
Kang-Yong Kim
Hyun Yoo Lee

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260505
Application Date: 20240910

Claims (20)

1 . An apparatus comprising: at least one memory array comprising multiple memory banks; at least one mode register configured to store a value indicative of a quantity of bits of communicated information that are allocated as error correction code (ECC) bits; and ECC circuitry coupled to the multiple memory banks and the at least one mode register, the ECC circuitry comprising multiple ECC engines and configured to: provide, by a first ECC engine of the multiple ECC engines, a first ECC value to a first memory bank of the multiple memory banks, the first ECC engine corresponding to the first memory bank; and provide, by a second ECC engine of the multiple ECC engines, a second ECC value to the first memory bank based on the value stored in the at least one mode register, the second ECC engine corresponding to the first memory bank and at least one other memory bank of the multiple memory banks.
2 . The apparatus of claim 1 , further comprising: an interface coupled to the ECC circuitry, the interface configured to: receive, on a first bus, data and a first portion of multiple bits of an ECC value corresponding to the data, a quantity of bits of the first portion of the multiple bits of the ECC value equal to the quantity of bits of communicated information that are allocated as ECC bits; and receive, on a second bus, a second portion of the multiple bits of the ECC value corresponding to the data.
3 . The apparatus of claim 2 , wherein the ECC circuitry is configured to: store the data in the first memory bank at a location allocated to data storage and at an address corresponding to the data; store the first portion of the multiple bits of the ECC value corresponding to the data in the first memory bank at the location allocated to data storage and at the address corresponding to the data; and store the second portion of the multiple bits of the ECC value corresponding to the data in the first memory bank at another location allocated to ECC value storage and at the address corresponding to the data.
4 . The apparatus of claim 1 , wherein the ECC circuitry is configured to: retrieve, from a first location of the first memory bank, data; retrieve, from the first location of the first memory bank, a first portion of multiple bits of an ECC value corresponding to the data, a quantity of bits of the first portion of the multiple bits of the ECC value equal to the quantity of bits of communicated information that are allocated as ECC bits; retrieve, from a second location of the first memory bank, a second portion of the multiple bits of the ECC value corresponding to the data, the second location different from the first location; combine the first portion of the multiple bits of the ECC value corresponding to the data and the second portion of the multiple bits of the ECC value corresponding to the data to produce reformed multiple bits of the ECC value; and perform an ECC determination using the data and the reformed multiple bits of the ECC value.
5 . A method comprising: receiving, by a memory device, a command indicative of a quantity of multiple bits for error correction code (ECC) values for a quantity of bits of data; receiving, by the memory device on a first bus, data and a first portion of multiple bits of an ECC value corresponding to the data; and receiving, by the memory device on a second bus, a second portion of the multiple bits of the ECC value corresponding to the data.
6 . The method of claim 5 , wherein: the first portion of the multiple bits of the ECC value corresponding to the data comprises a first quantity of ECC bits; the second portion of the multiple bits of the ECC value corresponding to the data comprises a second quantity of ECC bits; and the quantity of multiple bits for ECC values for the quantity of bits of data is equal to a sum of the first quantity of ECC bits and the second quantity of ECC bits.
7 . The method of claim 6 , wherein: the first bus comprises a data bus coupled between the memory device and a host device; and the second bus comprises a read strobe line coupled between the memory device and the host device.
8 . The method of claim 5 , further comprising: writing, by the memory device, a value in at least one mode register responsive to the receiving of the command, the value indicative of the quantity of multiple bits for ECC values for the quantity of bits of data.
9 . The method of claim 8 , further comprising: receiving, by the memory device from a host device, a mode register write command to activate a byte mode at the memory device; and writing, by the memory device, another value in at least one other mode register responsive to the receiving of the mode register write command, the other value indicative that the byte mode is active at the memory device.
10 . The method of claim 5 , further comprising: determining, by the memory device, a determined ECC value based on the received data; comparing, by the memory device, the determined ECC value to the first portion and the second portion of the multiple bits of the ECC value corresponding to the data; and performing, by the memory device, an operation based on the comparing.
11 . The method of claim 10 , wherein the performing comprises at least one of: correcting, by the memory device, a detected error in the data using the data, the first portion of the multiple bits of the ECC value corresponding to the data, and the second portion of the multiple bits of the ECC value corresponding to the data; or storing, by the memory device in at least one memory array, the data, the first portion of the multiple bits of the ECC value corresponding to the data, and the second portion of the multiple bits of the ECC value corresponding to the data.
12 . The method of claim 5 , further comprising: storing, by the memory device, the data in at least one memory array at a location allocated to data storage and at an address corresponding to the data; storing, by the memory device, the first portion of the multiple bits of the ECC value corresponding to the data in the at least one memory array at the location allocated to data storage and at the address corresponding to the data; and storing, by the memory device, the second portion of the multiple bits of the ECC value corresponding to the data in the at least one memory array at another location allocated to ECC value storage and at the address corresponding to the data.
13 . A method comprising: transmitting, by a host device, a command indicative of a quantity of multiple bits for error correction code (ECC) values for a quantity of bits of data; transmitting, by the host device on a first bus, data and a first portion of multiple bits of an ECC value corresponding to the data; and transmitting, by the host device on a second bus, a second portion of the multiple bits of the ECC value corresponding to the data.
14 . The method of claim 13 , wherein: the first bus comprises a data bus coupled between the host device and a memory device.
15 . The method of claim 14 , wherein: the second bus comprises a read strobe line coupled between the host device and the memory device.
16 . The method of claim 13 , wherein the transmitting of the command indicative of the quantity of multiple bits for ECC values comprises: transmitting, by the host device to a memory device, a mode register write command to write a value in at least one mode register of the memory device, the value indicative of the quantity of multiple bits for ECC values for the quantity of bits of data.
17 . The method of claim 13 , wherein: the first portion of the multiple bits of the ECC value corresponding to the data comprises a first quantity of ECC bits; the second portion of the multiple bits of the ECC value corresponding to the data comprises a second quantity of ECC bits; and the quantity of multiple bits for ECC values for the quantity of bits of data is equal to a sum of the first quantity of ECC bits and the second quantity of ECC bits.
18 . The method of claim 17 , wherein: the sum of the first quantity of ECC bits and the second quantity of ECC bits equals ten (10), twelve (12), or fourteen (14); and the second quantity of ECC bits is eight (8).
19 . The method of claim 18 , wherein: the first quantity of ECC bits is two (2), four (4), or six (6); and the quantity of bits of data is 126, 124, or 122, respectively.
20 . The method of claim 13 , further comprising: transmitting, by the host device to a memory device, a mode register write command to activate a byte mode at the memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is a continuation of and claims priority to U.S. Non-Provisional patent application Ser. No. 17/654,354, filed on 10 Mar. 2022, which in turn claims the benefit of U.S. Provisional Patent Application No. 63/162,139, filed 17 Mar. 2021, the disclosures of which are hereby incorporated by reference herein in their entireties. BACKGROUND Computers, smartphones, and other electronic devices rely on processors and memories. A processor executes code based on data to run applications and provide features to a user. The processor obtains the code and the data from a memory. The memory in an electronic device can include volatile memory (e.g., random access memory (RAM)) and nonvolatile memory (e.g., flash memory). Volatile memory can include static RAM (SRAM) and dynamic RAM (DRAM). Like the number of cores or speed of a processor, memory characteristics that vary by memory type can impact an electronic device's performance. Memory demands in electronic devices continue to evolve and grow. For example, as manufacturers engineer processors to execute code faster, processors benefit from accessing memories more quickly. Applications on electronic devices may also operate on ever-larger data sets that require ever-larger memories. Further, manufacturers may seek physically smaller memories with smaller process technologies as the form factors of portable electronic devices continue to shrink. Accommodating these various demands is complicated by a growing demand to improve the accurate storing and retrieval of data by memories. BRIEF DESCRIPTION OF THE DRAWINGS This document describes apparatuses and techniques for configurable error correction code (ECC) circuitry with reference to the following drawings. The same numbers are used throughout the drawings to reference like features and components: FIG. 1 illustrates example apparatuses that can implement configurable ECC circuitry and schemes; FIG. 2 illustrates an example computing system that can implement aspects of configurable ECC circuitry and schemes with a memory device; FIG. 3 illustrates an example memory device; FIG. 4 illustrates an example architecture of a memory device that includes configurable ECC circuitry coupled to a memory array with multiple memory banks; FIG. 5 illustrates an example architecture for a memory device that includes configurable ECC circuitry and multiple memory banks; FIG. 6 illustrates an example architecture for a memory device that includes configurable ECC circuitry, multiple memory banks, and one or more internal data buses; FIGS. 7-1 through 7-4 illustrate example operations of configurable ECC circuitry and schemes for read operations and write operations in accordance with example protocols; FIGS. 8 and 9 illustrate example timing diagrams depicting aspects of configurable error correction; and FIGS. 10 through 12 illustrate flow diagrams of example processes that implement configurable ECC circuitry and schemes. DETAILED DESCRIPTION Overview Processors and memory work in tandem to provide features on computers and other electronic devices, including smartphones. An electronic device can generally provide enhanced features, such as high-resolution graphics and artificial intelligence, as a processor-and-memory tandem operate faster. Advances in processors have often outpaced those in memory. As a result, memory can cause a bottleneck during execution due to the disparity in speed between processors and memory. To counterbalance the faster operational speed of processors, computer engineers have developed several techniques to improve memory performance. One such technique involves accessing multiple memories in parallel. Manufacturers can design a memory device with multiple memory banks to enable parallel accessing. The memory device can access each memory bank in parallel with one or more other memory banks, multiplying the data-access rate. Consider that each memory bank of a four-banked memory device can read a byte of data substantially simultaneously. The four-banked memory device may then produce four bytes of data in the same time that a non-banked memory produces only one byte of data. Access circuitry or logic associated with each memory bank can operate separately, at least in part, from the access circuitry of other memory banks to enable simultaneous data reading (e.g., extracting a byte of information from memory cells). As a result, the memory device may replicate access circuitry for each memory bank of multiple memory banks. Manufacturers of memory devices position the replicated access circuitry proximate to each memory bank to reduce data-reading latency. Co-locating access circuitry and memory banks, however, can constrain systems and techniques that are used for memory safety and reliability, including error correction and detection using error-correction-code (ECC) technology. This Overview further describes ECC technology after introducing e