US-12619496-B2 - Apparatuses and methods for bounded fault compliant metadata storage

US12619496B2US 12619496 B2US12619496 B2US 12619496B2US-12619496-B2

Abstract

Apparatuses, systems, and methods for bounded fault compliant metadata storage. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. The first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other.

Inventors

Sujeet Ayyapureddi

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260505
Application Date: 20240126

Claims (20)

1 . An apparatus comprising: a first pair of data terminals configured to receive a first portion of a plurality of data bits and a first portion of a plurality of metadata bits; a second pair of data terminals configured to receive a second portion of the plurality of data bits and a second portion of the plurality of metadata bits; and a memory array comprising: a first column plane configured to store the first portion of the plurality of metadata bits; and a second column plane configured to store the second portion of the plurality of metadata bits, wherein the first column plane and the second column plane are not coupled to a same sub-word line driver.
2 . The apparatus of claim 1 , wherein the memory array includes a plurality of column planes which include the first column plane and the second column plane, and wherein the plurality of data bits is stored in the plurality of column planes.
3 . The apparatus of claim 2 , wherein during a write operation the plurality of data bits are written to the plurality of column planes in a first access pass, and wherein the plurality of metadata bits are written to the first column plane and the second column plane in a second access pass.
4 . The apparatus of claim 2 , further comprising an error correction code (ECC) circuit configured to generate a plurality of a parity bits based on the plurality of data bits and the plurality of metadata bits, wherein the plurality of parity bits are stored in an extra column plane of the memory array.
5 . The apparatus of claim 1 , wherein the apparatus is a memory device on a memory module which operates in a 5×2p4 architecture.
6 . The apparati s of claim 1 , wherein the plurality of data bits is 128 data bits and the plurality of metadata bits is 8 metadata bits.
7 . A memory module comprising an error correction memory device; a plurality of pseudo-channels, each pseudo-channel comprising a first pair of data terminals and a second pair data terminals; and a plurality of memory devices, each associated with at least one of the plurality of pseudo-channels, each of the plurality of memory devices comprising a plurality of column planes, wherein during a write operation at least one of the plurality of memory devices is configured to receive a first portion of a plurality of data bits and a first portion of a plurality of metadata bits along the first pair of data terminals in the associated at least one of the plurality of pseudo-channels and receive a second portion of the plurality of data bits and a second portion of the plurality of metadata bits along the second pair of data terminals in the associated at least one of the plurality pseudo-channels, wherein the plurality of data bits are stored in the plurality of column planes as part of a first access pass, and wherein the first portion of the plurality of metadata bits are stored in a first one of the plurality of column planes and the second portion of the plurality of metadata bits are stored in a second one of the plurality of column planes as part of a second access pass.
8 . The memory module of claim 7 , wherein the memory module is configured in a 5×2p4 configuration.
9 . The memory module of claim 7 , wherein the plurality of data bits is 128 data bits and the plurality of metadata bits is 8 metadata bits.
10 . The memory module of claim 7 , wherein the first one of the plurality of column planes is remote from the second one of the plurality of column planes.
11 . The memory module of claim 7 , wherein the error correction memory device is configured to enable the correction of up to the first pair of data terminals or the second pair of data terminals in one of the plurality of pseudo-channels.
12 . The memory module of claim 7 , wherein as part of a read operation the at least one of the plurality of memory devices is configured to read the plurality of metadata bits as part of a first access pass and configured to read the plurality of data bits as part of a second access pass.
13 . A method comprising: receiving a first set of metadata bits and a first set of data bits along a first pair of input/output terminals; receiving a second set of metadata bits and a second set of data bits along a second pair of input/output terminals; writing the first set of data bits and the second set of data bits to a plurality of column planes as part of a first access pass; and writing the first set of metadata bits to a selected first one of the plurality of column planes and writing the second set of metadata bits to a selected second one of the plurality of column planes as part of a second access pass.
14 . The method of claim 13 , further comprising providing a first column select value as part of the first access pass and providing a second column select value as part of the second access pass.
15 . The method of claim 13 , wherein the selected first one of the plurality of column planes and the selected second one of the plurality of column planes are remote each other.
16 . The method of claim 13 , further comprising: activating a first sub-word line driver associated with the selected first one of the plurality of column planes; and activating a second sub-word line driver associated with the selected second one of the plurality of column planes.
17 . The method of claim 13 , further comprising: generating a plurality of parity bits based on the first and the second set data bits and the first and the second set of metadata bits; and storing the parity bits in an extra column plane as part of the first access pass.
18 . The method of claim 13 , wherein the first set and the second set of metadata bits each include 4 bits for a total of 8 bits across the first and the second set of metadata bits, and wherein the first set and the second set of data bits each include 64 bits for a total of 128 bits across the first and the second set of data bits.
19 . The method of claim 13 , further comprising: providing a column select signal to the selected first one of the plurality of column planes and the selected second one of the plurality of column planes, wherein the column select signal is associated with a first number of bit lines in the selected first one and the selected second one of the plurality of column planes; and providing a write enable signal to a portion of the first number of bit lines in the selected first one and the selected second one of the plurality of column planes.
20 . An apparatus comprising: a first pair of data terminals configured to receive a first portion of a plurality of data bits and a first portion of a plurality of metadata bits; a second pair of data terminals configured to receive a second portion of the plurality of data bits and second portion of the plurality of metadata bits; and a memory array comprising: a first column plane configured to store the first portion of the plurality of metadata bits; and a second column plane configured to store the second portion of the plurality of metadata bits, wherein the apparatus is a memory device on a memory module which operates in a 5×2p4 architecture.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the filing benefit of U.S. Provisional Application No. 63/482,487, filed Jan. 31, 2023. This application is incorporated by reference herein in its entirety and for all purposes. BACKGROUND This disclosure relates generally to semiconductor devices, and more specifically to semiconductor memory devices. In particular, the disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information may be stored on individual memory cells of the memory as a physical signal (e.g., a charge on a capacitive element). During an access operation, an access command may be received along with address information which specifies which memory cells should be accessed. There is a growing interest in enabling the memory to store information in the array which is associated with pieces of data. For example, error correction information and/or metadata may be stored in the array along with their associated data. Memory modules may be capable of correcting certain sets of information. There may be a need to ensure that when metadata is used, the metadata does not extend across multiple sets, preventing correction. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a memory system according to some embodiments of the present disclosure. FIG. 2 is a block diagram of a semiconductor device according an embodiment of the disclosure. FIG. 3 is a block diagram of a memory device according to some embodiments of the present disclosure. FIG. 4 is a flow chart of a method of writing data and metadata to a memory device according to some embodiments of the present disclosure. FIG. 5 is a block diagram of data and metadata bursts in a 5×2p4 architecture with 4 bytes of metadata according to some embodiments of the present disclosure. FIG. 6 is a block diagram of a memory array according to some embodiments of the present disclosure. FIG. 7 is a flow chart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure or its applications or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings which form a part hereof, and which are shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the disclosure. Moreover, for the purpose of clarity, detailed descriptions of certain features will not be discussed when they would be apparent to those with skill in the art so as not to obscure the description of embodiments of the disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the disclosure is defined only by the appended claims. Memory arrays may generally include a number of memory cells arranged at the intersection of word lines (rows) and bit lines/digit lines (columns). The columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns within each of the active column planes to provide data. When an access command is received, the memory may prefetch a codeword (e.g., a number of bits of data) along with one or more associated bits from the memory and either replace the prefetched data with new data (e.g., as part of a write operation) or provide the prefetched data off the memory device (e.g., as part of a read operation). Memory devices may store additional information which is associated with each codeword. For example, the additional information may include parity bits which are used as part of an error correction scheme, metadata which includes information about the data codeword (or is a portion of information about a larger set of data which includes the codeword), or combinations thereof. As used herein, the term data may represent any bits of information that the controller wishes to store and/or retrieve from the memory. The term metadata may represent any bits of information about the data which the controller writes to and/or receives from the memory. For example, the metadata may be information that the controller generates about the data, about how or where the data memory is stored in the memory, about how many errors have been detected in the data, etc. The data and the metadata together represent information written to the memory by a controller and then also read from the memory by the controller, with the data and metadata differing in content and how they are generated in that the metadata is bas