US-12619509-B1 - Integrated circuit test pattern interleaving

Abstract

At least one processor may obtain a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. The at least one processor may next generate a test data sequence including an interleaving of respective task procedures of the plurality of test pattern data sets, where the generating of the test data sequence includes generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving. The at least one processor may then apply the test data sequence via the shared testing input bus.

Inventors

• Denis Martin
• Bala Tarun Nelapatla

Assignees

• SYNOPSYS, INC.

Dates

Publication Date

20260505

Application Date

20231109

Claims (19)

1. 1 . A method comprising: obtaining a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus; generating, by a processing device, a test data sequence comprising an interleaving of respective task procedures of the plurality of test pattern data sets, wherein the generating of the test data sequence comprises generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving, and wherein each sleep instruction of the sleep instructions indicates a number of clock cycles of a test clock for a respective core of the plurality of cores to ignore the test data sequence via the shared testing input bus; and applying the test data sequence via the shared testing input bus.
2. 2 . The method of claim 1 , wherein the shared testing input bus comprises a scan input bus.
3. 3 . The method of claim 1 , wherein each task procedure of the task procedures comprises an instruction.
4. 4 . The method of claim 3 , wherein at least one task procedure of the task procedures further comprises a payload.
5. 5 . The method of claim 3 , wherein the instruction comprises an operation code.
6. 6 . The method of claim 1 , wherein a respective sleep instruction for a respective core of the plurality of cores is included in the test data sequence in association with each task procedure of the task procedures.
7. 7 . The method of claim 1 , wherein each core of the plurality of cores is initialized with a respective sleep counter value indicating a number of clock cycles to sleep with respect to the test clock prior to obtaining an initial instruction.
8. 8 . The method of claim 1 , wherein the generating of the test data sequence is in accordance with a scheduling method.
9. 9 . The method of claim 1 , wherein the interleaving comprises: allocating at least a first task procedure for a first core of the plurality of cores to the test data sequence; and allocating at least a second task procedure for a second core of the plurality of cores to the test data sequence following the at least the first task procedure within the test data sequence.
10. 10 . The method of claim 9 , wherein the generating of the sleep instructions for the respective cores of the plurality of cores comprises: selecting a number of sleep cycles for the second core based upon a first number of clock cycles of the at least the first task procedure; and selecting a number of sleep cycles for the first core based upon a second number of clock cycles of the at least the second task procedure.
11. 11 . The method of claim 1 , wherein each test pattern data set of the plurality of test pattern data sets comprises a series of alternating one or more task procedures of the task procedures and whitespace data.
12. 12 . The method of claim 11 , wherein the whitespace data comprises at least one clock cycle in a test pattern data set of the plurality of test pattern data sets in which data values are irrelevant for a respective core associated with the test pattern data set.
13. 13 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor of a first core of a plurality of cores of an integrated circuit, cause the processor to: obtain at least a first procedure via a shared testing input bus that is shared among the plurality of cores in a scan test group, the at least the first procedure comprising at least a first instruction; perform at least a first task in accordance with the at least the first instruction; obtain, via the shared testing input bus, a sleep instruction comprising a number of clock cycles to ignore data on the shared testing input bus; and obtain at least a second procedure via the shared testing input bus, in response to a completion of the number of clock cycles, the at least the second procedure comprising at least a second instruction, wherein at least one additional procedure for another core of the plurality of cores is presented on the shared testing input bus between the at least the first procedure and the at least the second procedure.
14. 14 . The non-transitory computer readable medium of claim 13 , wherein the stored instructions further cause the processor to: count the number of clock cycles in accordance with the sleep instruction.
15. 15 . The non-transitory computer readable medium of claim 14 , wherein stored instructions cause the processor to count the number of clock cycles by: loading at least a first counter with the number of clock cycles; and for each clock cycle of a test clock, decrementing the at least the first counter.
16. 16 . The non-transitory computer readable medium of claim 15 , wherein the at least the first instruction includes a first procedure duration of the first procedure, wherein the stored instructions further cause the processor to: set the at least the first counter with the first procedure duration, wherein the performing of the at least the first task spans the first procedure duration, and wherein the at least the first counter is decremented for each clock cycle of a plurality of clock cycles of a test clock.
17. 17 . The non-transitory computer readable medium of claim 13 , wherein the at least the first instruction comprises a load instruction, and wherein the at least the first task comprises: loading at least one register with data from the shared testing input bus; or passing data from the shared testing input bus to the first core.
18. 18 . The non-transitory computer readable medium of claim 13 , wherein the at least the first instruction comprises an unload instruction, wherein the performing of the at least the first task includes performing an unload operation in accordance with the at least the first instruction, and wherein the unload operation is performed with a delay defined in an offset value that is preloaded into the first core.
19. 19 . A circuit comprising: a finite state machine to track state changes of the circuit in accordance with a procedure counter and instructions from a shared testing input bus, wherein the shared testing input bus is shared among a plurality of cores, wherein the circuit is associated with a first core of the plurality of cores, and wherein the finite state machine is placed into a sleep state in response to a sleep instruction on the shared testing input bus; the procedure counter to obtain counter values from the instructions on the shared testing input bus and to decrement the counter values in accordance with a test clock, wherein the procedure counter counts down a number of clock cycles in accordance with the sleep instruction when the finite state machine is placed into the sleep state; and a multiplexer including at least: an input port for the shared testing input bus; and a first select line that is controlled by the finite state machine, wherein the multiplexer is to pass data on the shared testing input bus to a codec of the first core when the finite state machine is in a load state.

Description

TECHNICAL FIELD The present disclosure generally relates to and electronic design automation (EDA) system. In particular, the present disclosure relates to automatic test pattern generation and circuit testing. BACKGROUND During test pattern generation, automatic test pattern generation (ATPG) systems apply data sequences via scan channels to scan chains and/or scan compression compressors and decompressors (codecs). ATPG systems may use various methods to maximize the utilization of scan channels and to generate test patterns that may efficiently test for various faults. SUMMARY In one example, the present disclosure describes a method, computer-readable medium, and apparatus for generating a test data sequence including an interleaving of respective procedures of a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. For instance, in one example, at least one processor may obtain a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. The at least one processor may next generate a test data sequence including an interleaving of respective task procedures of the plurality of test pattern data sets, where the generating of the test data sequence includes generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving. The at least one processor may then apply the test data sequence via the shared testing input bus. In one example, the present disclosure also describes a method, computer-readable medium, and apparatus for performing tasks in response to procedures obtained via a shared testing input bus according to sleep instructions including a number of clock cycles to ignore data on the shared testing input bus. For instance, a processor of a first core of an integrated circuit may obtain at least a first procedure via a shared testing input bus that is shared among a plurality of cores in a scan test group including the first core, the at least the first procedure including at least a first instruction. The processor may next perform at least a first task in accordance with the at least the first instruction. In addition, the processor may obtain, via the shared testing input bus, a sleep instruction including a number of clock cycles to ignore data on the shared testing input bus. The processor may then obtain at least a second procedure via the shared testing input bus, in response to a completion of the number of clock cycles, the at least the second procedure including at least a second instruction. In one example, the present disclosure further describes a circuit including a finite state machine to track state changes of the circuit module in accordance with a procedure counter and instructions from a shared testing input bus, where the shared testing input bus is shared among a plurality of cores, and where the circuit is associated with a first core of the plurality of cores. The circuit may further include the procedure counter, to obtain counter values from instructions on the shared testing input bus and to decrement the counter values in accordance with a test clock, and a multiplexer including at least an input port for the shared testing input bus and a first select line that is controlled by the finite state machine, where the multiplexer is to pass data on the shared testing input bus to a codec of the first core when the finite state machine is in a load state. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the present disclosure. The figures are used to provide knowledge and understanding of embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale. FIG. 1 illustrates aspects of a circuit including a test/scan group having two block/cores and further illustrates examples of interleaving of procedures from different test pattern data sets; FIG. 2 illustrates an example test pattern data set for an individual block/core and a representation of a test data pattern set along with the statuses of an input bus and an output bus during various tasks of the test data pattern set; FIG. 3 illustrates an example timing diagram for two block/cores and a test data sequence for an example of two blocks/cores; FIG. 4 illustrates an example scheduling phase for five test pattern data sets for respective blocks/cores; FIG. 5 illustrates an example protocol decoder (e.g., a circuit module, or a portion thereof); FIG. 6 illustrates a flowchart of an example method for generating a test data sequence including an interleaving of respective procedures of a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be appl