US-12619510-B2 - Double data rate channel sensitivity and dual in-line memory module population optimization

Abstract

An information handling system comprising a first input/output (I/O) device and a Basic Input/Output System (BIOS) configured to perform a first I/O health check of the first I/O device and to gather a first I/O health check data from the first I/O health check performed. The information handling system also includes a processor configured to calculate a first set of deltas between a first set of channel margins associated with the first I/O device based on the first I/O health check data and expected channel margins and determine whether the first set of deltas is within the expected channel margins for the first I/O device. When the first set of deltas is within the expected channel margins, then identify the first I/O device as healthy. When the first set of deltas is not within the expected channel margins, then identify the first I/O device as unhealthy.

Inventors

• Douglas Winterberg
• Bhyrav Mutnury

Assignees

• DELL PRODUCTS L.P.

Dates

Publication Date

20260505

Application Date

20240619

Claims (20)

1. 1 . An information handling system comprising: a first input/output (I/O) device; a Basic Input/Output System (BIOS) configured to perform a first I/O health check of the first I/O device and to gather a first I/O health check data from the first I/O health check performed; and a processor configured to: calculate a first set of deltas between a first set of channel margins associated with the first I/O device based on the first I/O health check data and expected channel margins; determine whether the first set of deltas is within the expected channel margins for the first I/O device; and when the first set of deltas is within the expected channel margins, then identify the first I/O device as healthy; when the first set of deltas is not within the expected channel margins, then identify the first I/O device as unhealthy; and calculate a second set of deltas between a second set of channel margins associated with a second I/O device based on the first I/O health check data and the expected channel margins.
2. 2 . The information handling system of claim 1 , wherein if there is an improvement between the first set of channel margins and the second set of channel margins, then retaining the first I/O device in a second memory socket and the second I/O device in a first memory socket.
3. 3 . The information handling system of claim 1 , wherein the processor is further configured to determine whether the second set of deltas is within the expected channel margins.
4. 4 . The information handling system of claim 3 , wherein when the second set of deltas is not withinin the expected channel margins, then identify the second I/O device as unhealthy.
5. 5 . The information handling system of claim 4 , wherein the first I/O device and the second I/O device are Dual In-Line Memory Modules.
6. 6 . The information handling system of claim 5 , wherein the first I/O device is seated in a first memory socket and the second I/O device is seated in a second memory socket.
7. 7 . The information handling system of claim 6 , wherein the BIOS is further configured to subsequent to a swap between the first I/O device and the second I/O device, perform a second I/O health check of the first I/O device and gather a second I/O health check data from the second I/O health check.
8. 8 . The information handling system of claim 7 , wherein the swap is performed when the first I/O device is unhealthy and the second I/O device is healthy.
9. 9 . The information handling system of claim 7 , wherein the processor is further configured to calculate a third set of deltas between a third set of channel margins associated with the first I/O device based on the second I/O health check data and the expected channel margins.
10. 10 . The information handling system of claim 9 , wherein the processor is further configured to determine whether there is an improvement between the first set of channel margins and the third set of channel margins.
11. 11 . The information handling system of claim 9 , wherein when there is an improvement between the first set of channel margins and the third set of channel margins, then retain the first I/O device in the second memory socket and the second I/O device in the first memory socket.
12. 12 . The information handling system of claim 9 , wherein when there is no improvement between the first set of channel margins and the third set of channel margins then re-swap the first I/O device and the second I/O device.
13. 13 . A method comprising: performing, by a processor, a first input/output (I/O) health check of a first I/O device; gathering a first I/O health check data from the first I/O health check performed; calculating a first set of deltas between a first set of channel margins associated with the first I/O device based on the first I/O health check data and expected channel margins; determining whether the first set of deltas are within the expected channel margins for the first I/O device; when the first set of deltas is within the expected channel margins, then identifying the first I/O device as healthy; when the first set of deltas is not within the expected channel margins, then identifying the first I/O device as unhealthy; and calculating a second set of deltas between a second set of channel margins associated with a second I/O device based on the first I/O health check data and the expected channel margins.
14. 14 . The method of claim 13 , wherein the first I/O device and a second I/O device are Dual In-Line Memory Modules.
15. 15 . The method of claim 14 , wherein the first I/O device is seated in a first memory socket and the second I/O device is seated in a second memory socket.
16. 16 . The method of claim 15 , further comprising subsequent to a swap between the first I/O device and the second I/O device, performing a second I/O health check of the first I/O device and gathering a second I/O health check data from the second I/O health check.
17. 17 . The method of claim 16 , further comprising determining whether there is an improvement between the first set of channel margins and the second set of channel margins.
18. 18 . The method of claim 16 , wherein if there is an improvement between the first set of channel margins and the second set of channel margins, then retaining the first I/O device in the second memory socket and the second I/O device in the first memory socket.
19. 19 . The method of claim 13 , further comprising determining whether the second set of deltas is within the expected channel margins.
20. 20 . A non-transitory computer-readable medium to store instructions that are executable to perform operations comprising: performing a first input/output (I/O) health check of a first I/O device and a second I/O device; gathering a first I/O health check data from the first I/O health check performed; calculating deltas between a first set of channel margins associated with the first I/O device based on the first I/O health check data and expected channel margins; calculating deltas between a second set of channel margins associated with the second I/O device based on the first I/O health check data and the expected channel margins of the first I/O device; when the deltas between the first set of channel margins is within the expected channel margins, then identifying the first I/O device as healthy; and when the deltas between the first set of channel margins is not within the expected channel margins, then identifying the first I/O device as unhealthy.

Description

FIELD OF THE DISCLOSURE The present disclosure generally relates to information handling systems, and more particularly relates to Double Data Rate (DDR) channel sensitivity and Dual In-line Memory Module (DIMM) population optimization. BACKGROUND As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, or communicates information or data for business, personal, or other purposes. Technology and information handling needs and requirements can vary between different applications. Thus, information handling systems can also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information can be processed, stored, or communicated. The variations in information handling systems allow information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems can include a variety of hardware and software resources that can be configured to process, store, and communicate information and can include one or more computer systems, graphics interface systems, data storage systems, networking systems, and mobile communication systems. Information handling systems can also implement various virtualized architectures. Data and voice communications among information handling systems may be via networks that are wired, wireless, or some combination. SUMMARY An information handling system comprising a first input/output (I/O) device and a Basic Input/Output System (BIOS) configured to perform a first I/O health check of the first I/O device and to gather a first I/O health check data from the first I/O health check performed. The information handling system also includes a processor configured to calculate a first set of deltas between a first set of channel margins associated with the first I/O device based on the first I/O health check data and expected channel margins and determine whether the first set of deltas is within the expected channel margins for the first I/O device. When the first set of deltas is within the expected channel margins, then identify the first I/O device as healthy. When the first set of deltas is not within the expected channel margins, then identify the first I/O device as unhealthy. BRIEF DESCRIPTION OF THE DRAWINGS It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the drawings herein, in which: FIG. 1 is a block diagram of an information handling system, according to an embodiment of the present disclosure; FIG. 2 is a flowchart of a method for Double Data Rate (DDR) channel sensitivity and Dual In-line Memory Module (DIMM) population optimization, according to an embodiment of the present disclosure; and FIG. 3 is a block diagram of a generalized information handling system, according to an embodiment of the present disclosure. The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION OF THE DRAWINGS The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The description is focused on specific implementations and embodiments of the teachings and is provided to assist in describing the teachings. This focus should not be interpreted as a limitation on the scope or applicability of the teachings. In general, information handling systems include a processing device, a memory device for storing computer code that when executed by the processor, causes the information handling system to perform various operations on data, and a data storing device for storing the data. Memory modules are often configured on a circuit card, often referred to as a DIMM. The information handling system includes various other pluggable circuit cards, such as Peripheral Component Interconnect (PCI) cards, DIMMs, etc. Certain information handling system devices, such as processing devices and pluggable circuit cards, generally plug into a connector slot or socket. The connector slot typically includes several metal connectors for contacting corresponding connector pads on the devices. With DDR speeds exceeding third-generation Peripheral Component Interconnect-Express (PCIe Gen3) speeds of 8-12+ gigabits per second (Gbps), interface margins, also referred to herein as channel margins, are becoming increasingly sensitiv