US-12619519-B2 - Apparatus and method for simulated virtual component development

US12619519B2US 12619519 B2US12619519 B2US 12619519B2US-12619519-B2

Abstract

An apparatus for, and method of, simulated virtual component testing, including a processor and a memory, the processor configured to receive a specification datum, receive an application datum, generate emulation parameters as a function of the specification datum, generate a testing framework as a function of the emulation parameters, determine an integration datum as a function of the testing framework and the application datum, output a compatibility datum as a function of the integration datum, and display a user interface.

Inventors

David Morse
David Walsh

Assignees

PARRY LABS, LLC

Dates

Publication Date: 20260505
Application Date: 20240315

Claims (12)

1 . An apparatus for simulated virtual component development, the apparatus comprising: at least a processor; and at least a memory communicatively connected to the at least a processor, wherein the at least a memory contains instructions configuring the at least a processor to: receive a specification datum; receive an application datum; generate emulation parameters as a function of the specification datum, wherein the emulation parameters comprise identification of an engineering methodology which includes a set of procedures to solve engineering problems, wherein the engineering methodology comprises an agile engineering technology; execute the agile engineering methodology by iteratively testing sub-components of a component included in the specification datum followed by testing of a whole component; generate a testing framework as a function of the emulation parameters and execution of the agile engineering methodology; determine an integration datum by inputting into an integration machine learning model the testing framework and the application datum and receiving as an output from the integration machine learning model the integration datum, wherein the integration datum is generated within a containerized environment including a container image, wherein the container image includes a portable executable image combined with a manifest file; output a compatibility datum as a function of the integration datum; generate an automated artifact as a function of compatibility datum, wherein the automated artifact comprises data objects including at least executable files; generate a deployment environment as a function of the automated artifact for further testing of the component, including its sub-components, wherein generating the deployment environment comprises: implementing context insertion through a vector database, wherein the vector database is used to provide additional information for generating deployment environment; and deploying the containerized environment; and a display device configured to display a user interface for the compatibility datum.
2 . The apparatus of claim 1 , wherein at least one of the emulation parameters is configured to generate a digital twin.
3 . The apparatus of claim 2 , wherein the digital twin is configured to simulate at least a specification datum.
4 . The apparatus of claim 1 , wherein the specification datum comprises a specification of a Field Programmable Gate Array.
5 . The apparatus of claim 1 , wherein the specification datum comprises a specification of a Boot Operating Storage Solution Card.
6 . The apparatus of claim 1 , wherein the user interface is configured to display at least a layer of structural detail of the specification datum.
7 . A method of simulated virtual component development, the method comprising: receiving, by at least a processor, a specification datum; receiving, by the at least a processor, an application datum; generating, by the at least a processor, emulation parameters as a function of the specification datum, wherein the emulation parameters comprise identification of an engineering methodology which includes a set of procedures to solve engineering problems, wherein the engineering methodology comprises an agile engineering technology; executing, by the at least a processor, the agile methodology by iteratively testing sub-components of a component included in the specification datum followed by testing of a whole component; generating, by the at least a processor, a testing framework as a function of the emulation parameters and execution of the agile engineering technology; determining, by the at least a processor, an integration datum by inputting into an integration machine learning model the testing framework and the application datum and receiving as an output from the integration machine learning model the integration datum, wherein the integration datum is generated within a containerized environment including a container image, wherein the container image includes a portable executable image combined with a manifest file; outputting, by the at least a processor, a compatibility datum as a function of the integration datum; generating, by the at least a processor, an automated artifact as a function of compatibility datum, wherein the automated artifact comprises data objects including at least executable files; generating, by the at least a processor, a deployment environment as a function of the automated artifact for further testing of the component, including its sub-components, wherein generating the deployment environment comprises: implementing context insertion through a vector database, wherein the vector database is used to provide additional information for generating deployment environment; and deploying the containerized environment; and displaying, by a display device, a user interface for the compatibility datum.
8 . The method of claim 7 , wherein the at least one of the emulation parameters is configured to generate a digital twin.
9 . The method of claim 8 , wherein the digital twin is configured to simulate at least a specification datum.
10 . The method of claim 7 , wherein the specification datum comprises a specification of a Field Programmable Gate Array.
11 . The method of claim 7 , wherein the specification datum comprises a specification of a Boot Operating Storage Solution Card.
12 . The method of claim 7 , wherein the user interface is configured to display at least a layer of structural detail of the specification datum.

Description

FIELD OF THE INVENTION The present invention generally relates to the field of circuit development and integration. In particular, the present invention is directed to engineering development support. BACKGROUND Testing compatibility in a system between software applications and electronic components is vital for proper integration and functioning of the system. However, there are circumstances where access to those components is limited. SUMMARY OF THE DISCLOSURE In an aspect an apparatus for virtual component testing includes at least a processor and a memory communicatively connected to the at least a processor, where the memory contains instructions configuring the at least a processor to receive a specification datum, receive an application datum, generate emulation parameters as a function of the specification datum, generate an testing framework as a function of the emulation parameters, determine an integration datum as a function of the testing framework and the application datum, output a compatibility datum as a function of the integration datum, and display a user interface. In another aspect a method of virtual component testing, wherein the method includes receiving a specification datum, receiving an application datum, generating emulation parameters as a function of the specification datum, generating a testing framework as a function of the emulation parameters, determining an integration datum as a function of the testing framework and the application datum, outputting a compatibility datum as a function of the integration datum, and displaying a user interface. These and other aspects and features of non-limiting embodiments of the present invention will become apparent to those skilled in the art upon review of the following description of specific non-limiting embodiments of the invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein: FIG. 1 is a representation of an apparatus for simulated virtual component development; FIG. 2 is a block diagram of an exemplary embodiment of a machine learning process; FIG. 3 is a diagram of an exemplary embodiment of a neural network; FIG. 4 is a diagram of an illustrative embodiment of a node of a neural network; FIG. 5 is an exemplary embodiment of a method for engineering development support; and FIG. 6 is a block diagram of a computing system that can be used to implement any one or more of the methodologies disclosed herein and any one or more portions thereof. The drawings are not necessarily to scale and may be illustrated by phantom lines, diagrammatic representations, and fragmentary views. In certain instances, details that are not necessary for an understanding of the embodiments or that render other details difficult to perceive may have been omitted. DETAILED DESCRIPTION At a high level, aspects of the present disclosure are directed to apparatus and methods for simulated virtual component development. In an embodiment, apparatus 100 may be used to create a full digital twin of a virtual component. Exemplary embodiments illustrating aspects of the present disclosure are described below in the context of several specific examples. Referring now to FIG. 1, an exemplary embodiment of an apparatus 100 for simulated virtual component development is illustrated. The apparatus 100 includes at least a processor 104. Processor 104 and at least a processor 104 are used interchangeably throughout this disclosure. Processor 104 may include, without limitation, any processor described in this disclosure. Processor 104 may be included in a computing device. Computing device may include any computing device as described in this disclosure, including without limitation a microcontroller, microprocessor, digital signal processor (DSP) and/or system on a chip (SoC) as described in this disclosure. Processor 104 may include, be included in, and/or communicate with a mobile device such as a mobile telephone or smartphone. Processor may include, and/or be included in, a single computing device operating independently, or may include two or more computing device operating in concert, in parallel, sequentially or the like; two or more computing devices may be included together in a single computing device or in two or more computing devices. Processor 104 may interface or communicate with one or more additional devices as described below in further detail via a network interface device. Network interface device may be utilized for connecting processor 104 to one or more of a variety of networks, and one or more devices. Examples of a network interface device include, but are not limited to, a network interface card (e.g., a mobile network interface card, a L