US-12619524-B2 - Storage controller for non-volatile memory device including trim command and mapping invalidation

US12619524B2US 12619524 B2US12619524 B2US 12619524B2US-12619524-B2

Abstract

An operation method of a storage controller configured to control a non-volatile memory device. The method including receiving a first write command for a first logical address included in a first logical address range corresponding to a first trim bit from an external host, the first trim bit being in an activated state when the first write command is received, performing a first mapping invalidation for the first logical address range in response to the first write command, before the first mapping invalidation is complete, receiving a second write command corresponding to a second logical address included in the first logical address range from the host, skipping a second mapping invalidation corresponding to the second write command, and after the first mapping invalidation is complete, performing a mapping update for the second logical address.

Inventors

Kyungsik UM
JongMin Kim
Minsik Oh
Donggil Kang
Kyungjune Cho
Yoon Soo KIM
Myunggwan JEONG

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20240809
Priority Date: 20240105

Claims (20)

1 . An operation method of a storage controller configured to control a non-volatile memory device, the method comprising: receiving a first write command for a first logical address included in a first logical address range corresponding to a first trim bit from an external host, the first trim bit being in an activated state in response to determining that the first write command is received; initiating a first mapping invalidation for the first logical address range in response to the first write command; before the first mapping invalidation is complete, receiving a second write command corresponding to a second logical address included in the first logical address range from the external host; skipping a second mapping invalidation corresponding to the second write command; and after the first mapping invalidation is complete, performing a mapping update for the second logical address.
2 . The operation method of claim 1 , wherein, in response to determining that the second write command is received, the first trim bit is in the activated state.
3 . The operation method of claim 1 , wherein the activated state of the first trim bit indicates that the first logical address range is targeted for mapping invalidation.
4 . The operation method of claim 1 , wherein the receiving of the first write command is performed after the first trim bit is activated and before the storage controller enters an idle time.
5 . The operation method of claim 2 , further comprising: after the first mapping invalidation is complete, performing a mapping update for the first logical address, wherein the mapping update for the second logical address is performed after the mapping update for the first logical address is complete.
6 . The operation method of claim 5 , wherein the storage controller includes: a hazard table including information about a logical address corresponding to a write command.
7 . The operation method of claim 6 , further comprising: after the receiving of the first write command, storing information corresponding to the first logical address in the hazard table.
8 . The operation method of claim 7 , further comprising: after the receiving of the second write command, determining that a hazard is caused by the second write command, based on the first trim bit being in the activated state and the information corresponding to the first logical address being present in the hazard table.
9 . The operation method of claim 6 , further comprising: after the first mapping invalidation is complete and the mapping update for the first logical address is performed, deleting information corresponding to the first logical address from the hazard table.
10 . The operation method of claim 2 , wherein the storage controller is configured to handle pieces of data corresponding to the first logical address range corresponding to the first trim bit of the activated state as invalid data.
11 . The operation method of claim 2 , wherein the first logical address range includes the first logical address and the second logical address, and wherein the method further comprises: in response to determining that the second write command is received, determining that a hazard is caused by the second write command based on the first mapping invalidation not being complete.
12 . A storage device, comprising: a non-volatile memory device; and a storage controller configured to control the non-volatile memory device, the storage controller configured to receive a first write command for a first logical address included in a first logical address range corresponding to a first trim bit from an external host, initiate a first mapping invalidation for the first logical address range in response to the first write command, receive a second write command corresponding to a second logical address included in the first logical address range from the external host before the first mapping invalidation is complete, skip a second mapping invalidation corresponding to the second write command, and perform a mapping update for the second logical address after the first mapping invalidation is complete.
13 . The storage device of claim 12 , wherein, in response to determining that the first write command is received, the first trim bit is in an activated state, and wherein, in response to determining that the second write command is received, the first trim bit is in the activated state.
14 . The storage device of claim 13 , wherein the storage controller includes: a hazard table including information about a logical address corresponding to a write command.
15 . The storage device of claim 14 , wherein, after the first write command is received, the storage controller is further configured to: store information corresponding to the first logical address in the hazard table.
16 . The storage device of claim 15 , wherein, after the second write command is received, the storage controller is further configured to: determine that a hazard is caused by the second write command based on the first trim bit being in the activated state and the information corresponding to the first logical address being present in the hazard table.
17 . The storage device of claim 12 , wherein the storage controller is further configured to: receive a third write command for a third logical address included in a second logical address range corresponding to a second trim bit from the external host while performing the first mapping invalidation; and in response to determining that the second trim bit is in an activated state at a time of receiving the third write command, perform third mapping invalidation for the second logical address range in response to the third write command.
18 . The storage device of claim 12 , wherein the storage controller is further configured to: receive a third write command for a third logical address included in a second logical address range corresponding to a second trim bit from the external host while performing the first mapping invalidation; and in response to determining that the second trim bit is in a deactivated state at a time of receiving the third write command, perform third mapping invalidation for the third logical address among logical addresses included in the second logical address range in response to the third write command.
19 . The storage device of claim 12 , wherein the storage controller is further configured to: perform a mapping update for the first logical address after the first mapping invalidation is complete; and perform a mapping update for the second logical address after the mapping update for the first logical address is complete.
20 . An operation method of a storage controller configured to communicate with a host and a non-volatile memory device, the method comprising: activating a first trim bit corresponding to a first logical address range in response to a trim command from the host; receiving a first write command for a first logical address included in the first logical address range from the host; initiating a first mapping invalidation for the first logical address range in response to the first write command; before the first mapping invalidation is complete, receiving a second write command corresponding to a second logical address included in the first logical address range from the host; in response to determining that the second write command is received, skipping a second mapping invalidation corresponding to the second write command, based on the first trim bit being in an activated state and the first mapping invalidation not being complete; completing the first mapping invalidation and performing a first mapping update for the first logical address; and after the first mapping update is complete, performing a mapping update for the second logical address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0002419 filed on Jan. 5, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND Example embodiments of the present inventive concepts described herein relate to semiconductor memories, and more particularly, relate to storage controllers configured to control non-volatile memory devices, operation methods thereof, and storage devices including the storage controllers. A semiconductor memory is classified as a volatile memory, which loses data stored therein when power is turned off, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM) or a nonvolatile memory, which retains data stored therein even when power is turned off, such as a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM). A host uses a memory and a storage device. When a file is deleted by the host, the host may not erase data corresponding to the file and may mark the data to indicate an un-use state. Even though the host marks the data to indicate the un-use state, the storage device may recognize the data corresponding to the deleted file as valid data. Accordingly, the host may transmit, provide, or send a trim command to the storage device. The trim command may be a command for providing notification that the data corresponding to the deleted file are invalid data. The storage device may recognize the data corresponding to the deleted file as invalid data in response to the trim command. For improvement of performance, it may be advantageous to provide a storage device which processes the trim command at high speed. SUMMARY Example embodiments of the present inventive concepts provide storage controllers configured to control non-volatile memory devices, operation methods thereof, and storage devices including the storage controllers. According to some example embodiments, an operation method of a storage controller configured to control a non-volatile memory device includes receiving a first write command for a first logical address included in a first logical address range corresponding to a first trim bit from an external host, the first trim bit being in an activated state when the first write command is received; performing a first mapping invalidation for the first logical address range in response to the first write command; before the first mapping invalidation is complete, receiving a second write command corresponding to a second logical address included in the first logical address range from the host; skipping a second mapping invalidation corresponding to the second write command; and after the first mapping invalidation is complete, performing a mapping update for the second logical address. According to some example embodiments, a storage device includes a non-volatile memory device, and a storage controller configured to control the non-volatile memory device. The storage controller configured to receive a first write command for a first logical address included in a first logical address range corresponding to a first trim bit from an external host, perform a first mapping invalidation for the first logical address range in response to the first write command, receive a second write command corresponding to a second logical address included in the first logical address range from the host before the first mapping invalidation is complete, skip a second mapping invalidation corresponding to the second write command, and perform a mapping update for the second logical address after the first mapping invalidation is complete. According to some example embodiments, an operation method of a storage controller configured to communicate with a host and a non-volatile memory device includes activating a first trim bit corresponding to a first logical address range in response to a trim command from the host; receiving a first write command for a first logical address included in the first logical address range from the host; initiating a first mapping invalidation for the first logical address range in response to the first write command; before the first mapping invalidation is complete, receiving a second write command corresponding to a second logical address included in the first logical address range from the host; when the second write command is received, skipping a second mapping invalidation corresponding to the second write command, based on the first trim bit being in an activated state and the first mapping invalidation not being complete; completing the first mapping invalidation and performing a first mapping update for the first logical address; and after the first mapping update is complete, performing a mapping update for the second logical address. BRIEF DESCRIPTION OF THE DRAWINGS The above and