US-12619525-B2 - Memory and operating method thereof

US12619525B2US 12619525 B2US12619525 B2US 12619525B2US-12619525-B2

Abstract

Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified random-column-access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses having a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the mode indicates read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the mode indicates write operation; and ending the random column access mode by receiving an invalid chip-enable-signal.

Inventors

Sibo Ma
Hong Hu
Yang Li
Jianzhong Zhao

Assignees

GIGADEVICE SEMICONDUCTOR INC.

Dates

Publication Date: 20260505
Application Date: 20240910
Priority Date: 20230925

Claims (20)

1 . A method for operating a memory, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address, and the access interface adopting a SPI protocol; the method comprising: starting a specified column access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses, wherein the multiple access addresses have a same row address and multiple column addresses; receiving a row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the specified column access mode indicates a read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the specified column access mode indicates a write operation; and ending the column access mode by receiving an invalid chip enable signal; wherein the amount of data read or to be written in response to each access address is equal to a burst length*8 bits, wherein the burst length is preset in a mode register; and/or the specified column access mode is started by receiving a predetermined command via the data/address multiplexing line, or started by a preset mode register.
2 . The method according to claim 1 , further comprising: before ending the column access mode, and after outputting or receiving data read or to be written in response to any previously received access address via the data/address multiplexing line, receiving one or more new column addresses via the data/address multiplexing line, and performing the read operation or write operation in response to the received new column addresses, wherein the total number of received column addresses is not limited.
3 . The method according to claim 2 , wherein, in the case where the specified column access mode indicates the read operation: a new column address is received between two pieces of data sequentially read and outputted respectively in response to two previously received access addresses; or, in the case where the specified column access mode indicates the write operation: a new column address is received each time after receiving data to be written in response to a previously received access address.
4 . The method according to claim 3 , wherein, after finishing outputting a piece of data read in response to one of the previously received access addresses, it waits for a first preset number of clock cycles before receiving the new column address, wherein the first preset number is preset in a mode register according to a time required for direction switching on the data/address multiplexing line and a frequency of the clock cycles.
5 . The method according to claim 1 , further comprising: presetting a number of the access addresses to be read/written in the column access mode; after starting the column access mode, sequentially receiving the row address and the preset number of column addresses in succession; and in the case where the specified column access mode indicates the read operation, sequentially outputting data read respectively in response to each of the received access addresses in succession, or in the case where the specified column access mode indicates the write operation, sequentially receiving data to be written respectively in response to each of the received access addresses in succession.
6 . The method according to claim 1 , wherein, during the period from the beginning of the first read/write operation to the end of the last read/write operation, a word line of the memory array corresponding to the received row address remains activated.
7 . The method according to claim 1 , wherein, it waits for a second preset number of clock cycles preset according to a frequency of the clock cycles, after finishing receiving the column address and before outputting or receiving the data read or to be written.
8 . A method for operating a memory, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address, and the access interface adopting a SPI protocol; the method comprising: starting a specified column access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses, wherein the multiple access addresses have a same row address and multiple column addresses; receiving a row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the specified column access mode indicates a read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the specified column access mode indicates a write operation; and ending the column access mode by receiving an invalid chip enable signal; before ending the column access mode, and after outputting or receiving data read or to be written in response to any previously received access address via the data/address multiplexing line, receiving one or more new column addresses via the data/address multiplexing line, and performing the read operation or write operation in response to the received new column addresses, wherein the total number of received column addresses is not limited; wherein, the timing for receiving the new column addresses is determined by a preset data amount for the previous read/write operation or a number of clock cycles required for the previous read/write operation, or determined by implementing handshake with a host via another transmission line included in the access interface.
9 . The method according to claim 2 , wherein, after outputting data read in response to any previously received access address and before receiving the new column addresses, it waits for at least a first preset number of clock cycles, which is preset according to a frequency of the clock cycles, to switch data transmission direction of the data/address multiplexing line, and during the first preset number of clock cycles the data/address multiplexing line is released to a high-impedance state.
10 . The method according to claim 1 , wherein, in the case of receiving the invalid chip enable signal when a read/write operation performed in response to the received column address is not completed, the column address whose corresponding read operation has not yet been started or the column address whose corresponding written data has not yet been received any is discarded, and part of the written data is discarded in the case that the write operation is in progress or the written data is being received, wherein the chip enable signal is received from a host via a chip enable line included in the access interface.
11 . The method according to claim 1 , wherein, the access interface further includes a transmission line, for outputting a signal for synchronizing sampling of the data output on the data/address multiplexing line in the case of the read operation, and for receiving a signal for masking the data received on the data/address multiplexing line in the case of the write operation; and/or the memory is a PSRAM or a Flash; and/or the number of the data/address multiplexing line is 2 N , and 2 N or 2 N+1 bits of data or address are output or received per clock cycle via the data/address multiplexing line, wherein N is a non-negative integer; and/or the order of the read or written data transmitted via the data/address multiplexing line is consistent with the order of the received addresses.
12 . A method for operating a memory, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address, and the access interface adopts a SPI protocol; the method comprises: starting a specified row access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses, wherein the multiple access addresses have multiple row addresses and multiple column addresses; receiving at least two access addresses via the data/address multiplexing line, wherein each of the access addresses includes a row address and a column address; outputting data read in response to the received access addresses via the data/address multiplexing line in the case where the specified row access mode indicates a read operation, or receiving data to be written in response to the received access addresses via the data/address multiplexing line in the case where the specified row access mode indicates a write operation; and ending the row access mode by receiving an invalid chip enable signal; the amount of data read or to be written in response to each access address is equal to a burst length*8 bits, wherein the burst length is preset in a mode register; and/or the specified row access mode is started by receiving a predetermined command via the data/address multiplexing line, or started by a preset mode register.
13 . The method according to claim 12 , further comprising: before ending the row access mode, and after outputting or receiving data read or to be written in response to any previously received access address via the data/address multiplexing line, receiving one or more new access addresses via the data/address multiplexing line, and performing the read operation or write operation in response to the received new access addresses, wherein the total number of received access addresses is not limited.
14 . The method according to claim 13 , wherein, a new access address is received between two pieces of data sequentially read and outputted respectively in response to two previously received access addresses, or between two pieces of data to be written sequentially received respectively in response to two previously received access addresses.
15 . The method according to claim 14 , wherein, after finishing outputting the piece of data read in response to a first access address of the two previously received access addresses, it waits for a first preset number of clock cycles before receiving the new access address, or the new access address is received after finishing receiving the data to be written in response to a first access address of the two previously received access addresses.
16 . The method according to claim 15 , wherein, after finishing receiving the new access address, it waits for a third preset number of clock cycles before starting to output data read in response to a second access address of the two previously received access addresses, or after finishing receiving the new access address, it starts to receive data to be written in response to a second access address of the two previously received access addresses.
17 . The method according to claim 16 , wherein, in the case where the specified row access mode indicates the read operation, the data/address multiplexing line is released to a high-resistance state during the first preset number of clock cycles and the third preset number of clock cycles; wherein the first preset number is preset in a mode register according to a time required for direction switching on the data/address multiplexing line and a frequency of the clock cycles; wherein the third preset number is preset in the mode register according to a time required for deactivating a word line corresponding to the first access address and activating a word line corresponding to the second access address, and the frequency of the clock cycles; wherein the operation of deactivating the word line corresponding to the first access address and activating the word line corresponding to the second access address is initiated before the outputting of the data read in response to the previously received first access address is completed.
18 . The method according to claim 12 , further comprising: presetting a number of the access addresses to be read/written in the row access mode; after starting the row access mode, sequentially receiving the preset number of access addresses in succession; and in the case where the specified row access mode indicates the read operation, sequentially outputting data read respectively in response to each of the received access addresses in succession, or in the case where the specified row access mode indicates the write operation, sequentially receiving data to be written respectively in response to each of the received access addresses in succession.
19 . The method according to claim 12 , wherein, outputting data for a preceding read operation via the data/address multiplexing line is performed at least partially in parallel with switching to a word line required for a subsequent read operation; or switching to a word line required for a subsequent write operation is initiated, before the receiving of data in response to a subsequent write operation via the data/address multiplexing line is completed.
20 . A memory comprising: a memory array; an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address; and a controller configured to control the memory to perform the method according to claim 1 .

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese patent application No. 202311244994.7 filed on Sep. 25, 2023, the disclosure of which is incorporated herein by reference in its entirety and for all purposes. TECHNICAL FIELD The disclosure herein relates to the field of storage, and in particular to a memory and an operation method thereof. BACKGROUND Memory usually plays an important role in electronic devices such as computers. There are many different types of memories, including, such as, Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Pseudo Static Random Access Memory (PSRAM), and flash memory. As the performance standards of electronic devices are getting higher, faster access to memory is often required. Thus, it is desirable to improve the access speed of the memory. SUMMARY According to an embodiment of the present disclosure, a method for operating a memory is provided, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address, the method comprising: starting a specified random column access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses, wherein the multiple access addresses have a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the specified random column access mode indicates a read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the specified random column access mode indicates a write operation; and ending the random column access mode by receiving an invalid chip enable signal. According to an embodiment of the present disclosure, a method for operating a memory is provided, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address, the method comprises: starting a specified random row access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses, wherein the multiple access addresses have random row addresses and random column addresses; receiving at least two access addresses via the data/address multiplexing line, wherein each of the access addresses includes a row address and a column address; outputting data read in response to the received access addresses via the data/address multiplexing line in the case where the specified random row access mode indicates a read operation, or receiving data to be written in response to the received access addresses via the data/address multiplexing line in the case where the specified random row access mode indicates a write operation; and ending the random row access mode by receiving an invalid chip enable signal. According to an embodiment of the present disclosure, a memory is provided, the memory comprising: a memory array; an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address; and a control component configured to control the memory to perform the method according to any of the previously described embodiments of the present disclosure. BRIEF DESCRIPTION OF FIGURES The above and other objects, features and advantages of the present disclosure will become more apparent from the more detailed description of the exemplary embodiments of the present disclosure taken in conjunction with the accompanying drawings, wherein the same reference numerals generally refer to the same parts in exemplary embodiments of the present disclosure. FIG. 1 illustrates an exemplary composition diagram of a memory according to an embodiment of the present disclosure. FIG. 2 illustrates a timing diagram of a read operation mode as an example of a random column access mode according to an embodiment of the present disclosure. FIG. 3 illustrates a timing diagram of a read operation mode as an example of a random column access mode according to an embodiment of the present disclosure. FIG. 4 illustrates a timing diagram of a write operation mode as an example of a random column access mode according to an embodiment of the present disclosure. FIG. 5 illustrates a timing diagram of a read operation mode as an example of a random row access mode according to an embodiment of the present disclosure. FIGS. 6 and 7 illustrate timing diagrams for two cases of a write operation mode as an example of a random row access mode according to an embodiment of the