US-12619527-B2 - Memory devices including logic non-volatile memory

Abstract

A memory device includes a first array of Non-Volatile Memory (NVM) cells, a second array of logic NVM cells, and a controller. The second array of logic NVM cells stores instructions for accessing the first array of NVM cells. The controller is configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells.

Inventors

• Vikas RANA
• Kalyan Chakravarthy Kavalipurapu

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20220830

Claims (20)

1. 1 . A memory device comprising: a first array of Non-Volatile Memory (NVM) cells connected to column decode circuitry and row decode circuitry; a second array of logic NVM cells storing instructions for accessing the first array of NVM cells and connected to a row driver and a column multiplexer; a controller configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells; sense amplifiers connected to the column multiplexer to read data stored in the second array of logic NVM cells; and program circuits connected to the column multiplexer to write data to the second array of logic NVM cells.
2. 2 . The memory device of claim 1 , wherein the controller is configured to execute the instructions in response to address signals and control signals from an external host device.
3. 3 . The memory device of claim 1 , wherein the controller is configured to update the instructions stored in the second array of logic NVM cells.
4. 4 . The memory device of claim 1 , wherein each memory cell of the second array of logic NVM cells comprises: a first transistor connected to a word line; and a second transistor connected to a data line, wherein a gate of the first transistor is directly connected to a gate of the second transistor to form a floating gate.
5. 5 . The memory device of claim 4 , wherein each memory cell of the second array of logic NVM cells further comprises: a third transistor connected to a select line and the second transistor.
6. 6 . The memory device of claim 1 , wherein the second array of logic NVM cells stores a single instruction in each page of the second array of logic NVM cells.
7. 7 . The memory device of claim 1 , further comprising: a timer/sequencer connected to the second array of logic NVM cells and the controller to control a sequence of memory operations and a timing of signals for the second array of logic NVM cells.
8. 8 . A memory device comprising: a first array of Non-Volatile Memory (NVM) cells connected to column decode circuitry and row decode circuitry, each NVM cell of the first array comprising a single transistor; a second array of logic NVM cells storing instructions for accessing the first array of NVM cells and connected to a row driver and a column multiplexer, each logic NVM cell of the second array comprising at least two transistors; a controller configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells; sense amplifiers connected to the column multiplexer to read data stored in the second array of logic NVM cells; and program circuits connected to the column multiplexer to write data to the second array of logic NVM cells.
9. 9 . The memory device of claim 1 , wherein the second array of NVM cells comprises: a plurality of groups of memory cells; and a plurality of data line join switches to selectively connect a respective group of the plurality of groups of memory cells to the column multiplexer.
10. 10 . The memory device of claim 1 , further comprising: a digital finite state machine (FSM) configured to control operations of the second array of logic NVM cells.
11. 11 . The memory device of claim 1 , further comprising: an analog supply multiplexer to selectively apply voltages to the second array of logic NVM cells to perform access operations in the second array of NVM cells.
12. 12 . The memory device of claim 1 , wherein the instructions comprise firmware instructions.
13. 13 . The memory device of claim 1 , wherein the second array of logic NVM cells stores instructions for accessing the first array of NVM cells for read operations, programming operations, and erase operations.
14. 14 . The memory device of claim 1 , wherein the first array of NVM cells comprises an array of flash memory cells.
15. 15 . The memory device of claim 14 , wherein the array of flash memory cells comprises an array of NAND memory cells.
16. 16 . A memory device comprising: a first array of Non-Volatile Memory (NVM) cells, each NVM cell of the first array comprising a single transistor; a second array of logic NVM cells storing instructions for accessing the first array of NVM cells, each logic NVM cell of the second array comprising at least two transistors; a controller configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells; sense amplifiers connected to the second array of logic NVM cells to read data stored in the second array of logic NVM cells; and program circuits connected to the second array of logic NVM cells to write data to the second array of logic NVM cells.
17. 17 . The memory device of claim 16 , wherein each logic NVM cell of the second array comprises: a first transistor connected to a word line; and a second transistor connected to a data line, wherein a gate of the first transistor is directly connected to a gate of the second transistor to form a floating gate.
18. 18 . The memory device of claim 17 , wherein each memory cell of the second array of logic NVM cells further comprises: a third transistor connected to a select line and the second transistor.
19. 19 . The memory device of claim 18 , wherein the first array of NVM cells comprises an array of NAND memory cells.
20. 20 . The memory device of claim 16 , wherein the second array of logic NVM cells stores instructions for accessing the first array of NVM cells for read operations, programming operations, and erase operations.

Description

TECHNICAL FIELD The present disclosure relates generally to memory and, in particular, in one or more embodiments, the present disclosure relates to instruction logic non-volatile memory (NVM) within flash memory devices. BACKGROUND Memories (e.g., memory devices) are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand. A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known. Flash memory may include ROM to store computer-readable executable instructions (e.g., firmware) for operating the flash memory. In addition, flash memory may include content-addressable memory (CAM) and static random access memory (SRAM) to store a limited set of firmware instructions that may be used to replace firmware instructions stored in the ROM. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a simplified block diagram of a memory device according to an embodiment. FIG. 1B is a simplified block diagram of another memory device according to an embodiment. FIG. 2 is a simplified block diagram of a memory in communication with a processor as part of an electronic system, according to an embodiment. FIG. 3 is a simplified block diagram of control logic including a logic non-volatile memory (NVM), according to an embodiment. FIGS. 4A and 4B are block diagrams of a logic NVM according to an embodiment. FIG. 5 is a timing diagram of a logic NVM read protocol according to an embodiment. FIGS. 6A and 6B are timing diagrams of a logic NVM write protocol according to an embodiment. FIGS. 7A and 7B are timing diagrams of a logic NVM erase protocol according to an embodiment. FIG. 8 is a schematic diagram of an array of logic NVM cells according to an embodiment. FIG. 9 is schematic layout diagram of an array of logic NVM cells according to an embodiment. FIGS. 10A and 10B are schematic diagrams of logic NVM cells according to other embodiments. DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. The term “conductive” as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term “connecting” as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting by a conductive path unless otherwise apparent from the context. Ranges might be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, a