US-12619528-B2 - Data storage device and method for configuring a memory to write a requested amount of data over the memory's lifetime

Abstract

A data storage device is provided comprising a memory and one or more processors. The memory comprises a plurality of blocks, wherein each block is configurable as a single-level cell (SLC) block or as a multi-level cell (MLC) block. The one or more processors, individually or in combination, are configured to: receive a request from a host, wherein the request indicates a total amount of data to be written in the memory during a lifetime of the memory; determine a first number of blocks of the plurality of blocks to configure as SLC blocks and a second number of blocks of the plurality of blocks to configure as MLC blocks in order to attempt to satisfy the request; configure the first number of blocks as SLC blocks; and configure the second number of blocks as MLC blocks. Other embodiments are provided.

Inventors

• Ramanathan Muthiah
• Narendhiran Chinnaanangur Ravimohan
• Ramkumar Ramamurthy

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260505

Application Date

20240118

Claims (20)

1. 1 . A data storage device comprising: a memory comprising a plurality of blocks, wherein each block is configurable as a single-level cell (SLC) block or as a multi-level cell (MLC) block, wherein a total amount of data that can be written in the memory during a lifetime of the memory is based on a capacity of each of the plurality of blocks and a number of program/erase cycles that each of the plurality of blocks can endure, and wherein an MLC block comprises a higher capacity but can endure fewer program/erase cycles as compared to an SLC block; and one or more processors, individually or in combination, configured to: receive a request from a host, wherein the request indicates a requested total amount of data to be written in the memory during the lifetime of the memory, wherein the requested total amount of data to be written in the memory during the lifetime of the memory is different from the number of program/erase cycles that each of the plurality of blocks can endure; determine a first number of blocks of the plurality of blocks to configure as SLC blocks and a second number of blocks of the plurality of blocks to configure as MLC blocks in order to attempt to satisfy the request, wherein increasing the first number of blocks increases the total amount of data that can be written in the memory during the lifetime of the memory but decreases a total capacity of the memory; configure the first number of blocks as SLC blocks; and configure the second number of blocks as MLC blocks.
2. 2 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to: determine a memory capacity resulting from the first number of blocks being configured as SLC blocks and the second number of blocks being configured as MLC blocks; and inform the host of the determined memory capacity.
3. 3 . The data storage device of claim 2 , wherein the first number of blocks are configured as SLC blocks and the second number of blocks are configured as MLC blocks in response to receiving approval from the host of the determined memory capacity.
4. 4 . The data storage device of claim 2 , wherein the one or more processors, individually or in combination, are further configured to: receive a file system update request from the host; and in response to receiving a file system update request from the host, designate the data storage device as having the determining memory capacity.
5. 5 . The data storage device of claim 1 , wherein the first and second numbers are determined using a data structure that associates a plurality of total amounts of data to be written in the memory during the lifetime of the memory with a plurality of capacities of the memory.
6. 6 . The data storage device of claim 5 , wherein the one or more processors, individually or in combination, are further configured to: dynamically populate the data structure based on SLC block size, MLC block size, SLC block endurance, and MLC block endurance.
7. 7 . The data storage device of claim 1 , wherein the request from the host comprises a selection of one of a plurality of options.
8. 8 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to: use block health metrics in determining the first and second numbers.
9. 9 . The data storage device of claim 1 , wherein the requested total amount of data is directly expressed in the request from the host.
10. 10 . The data storage device of claim 1 , wherein the requested total amount of data is indirectly expressed in the request from the host.
11. 11 . The data storage device of claim 10 , wherein the requested total amount of data is indirectly expressed using a configuration scale.
12. 12 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.
13. 13 . A method comprising: performing in a data storage device comprising a memory comprising a plurality of memory areas, each memory area being configurable as a single-level cell (SLC) memory area or as a multi-level cell (MLC) memory area: receiving, from a host, an indication of an amount of data to be stored in the memory over a plurality of write cycles; determining a ratio of SLC-to-MLC memory areas to attempt to store the indicated amount of data in the memory over the plurality of write cycles, wherein increasing the ratio of SLC-to-MLC memory areas increases a total amount of data that can be stored in the memory over the plurality of write cycles but decreases a total capacity of the memory, and wherein the total amount of data that can be stored in the memory over the plurality of write cycles is different from a number of write cycles that each of the plurality of memory areas can endure; and configuring the memory according to the determined ratio of SLC-to-MLC memory areas.
14. 14 . The method of claim 13 , wherein the ratio of SLC-to-MLC memory areas is determined using a data structure that associates a plurality of amounts of data with a plurality of capacities of the memory.
15. 15 . The method of claim 14 , further comprising dynamically populating the data structure based on SLC memory area size, MLC memory area size, SLC memory area endurance, and MLC memory area endurance.
16. 16 . The method of claim 13 , further comprising: determining a memory capacity resulting from the determined ratio of SLC-to-MLC memory areas; and informing the host of the determined memory capacity.
17. 17 . The method of claim 16 , wherein the memory is configured according to the determined ratio of SLC-to-MLC memory areas in response to receiving approval from the host of the determined memory capacity.
18. 18 . The method of claim 16 , further comprising: receiving a file system update request from the host; and in response to receiving a file system update request from the host, designating the data storage device as having the determining memory capacity.
19. 19 . The method of claim 13 , wherein the indication is expressed using a configuration scale.
20. 20 . A data storage device comprising: a memory comprising a plurality of blocks, wherein each block is configurable as a single-level cell (SLC) block or as a multi-level cell (MLC) block, wherein a total amount of data that can be written in the memory is based on a capacity of each of the plurality of blocks and a number of program/erase cycles that each of the plurality of blocks can endure, and wherein an MLC block comprises a higher capacity but can endure fewer program/erase cycles as compared to an SLC block; and means for dynamically negotiating, with a host, a configuration of the memory that trades-off the total amount of data that can be written in the memory with a total capacity of the memory, wherein increasing a number of blocks that are configured as SLC blocks increases the total amount of data that can be written in the memory but decreases the total capacity of the memory, wherein the total amount of data that can be written in the memory is different from the number of program/erase cycles that each of the plurality of blocks can endure.

Description

BACKGROUND A data storage device can be used to store data in its memory. The memory of some data storage devices can be configured to include single-level cell (SLC) blocks and/or multi-level cell (MLC) blocks, which have different performance characteristics. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram of a data storage device of an embodiment. FIG. 1B is a block diagram illustrating a storage module of an embodiment. FIG. 1C is a block diagram illustrating a hierarchical storage system of an embodiment. FIG. 2A is a block diagram illustrating components of the controller of the data storage device illustrated in FIG. 1A according to an embodiment. FIG. 2B is a block diagram illustrating components of the data storage device illustrated in FIG. 1A according to an embodiment. FIG. 3 is a block diagram of a host and a data storage device of an embodiment. FIG. 4 is a block diagram of a host and a data storage device controller of an embodiment. FIG. 5 is an illustration of a configuration scale of an embodiment. DETAILED DESCRIPTION The following embodiments generally relate to a data storage device and method for configuring a memory to write a requested amount of data over the memory's lifetime. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises a plurality of blocks, wherein each block is configurable as a single-level cell (SLC) block or as a multi-level cell (MLC) block. The one or more processors, individually or in combination, are configured to: receive a request from a host, wherein the request indicates a total amount of data to be written in the memory during a lifetime of the memory; determine a first number of blocks of the plurality of blocks to configure as SLC blocks and a second number of blocks of the plurality of blocks to configure as MLC blocks in order to attempt to satisfy the request; configure the first number of blocks as SLC blocks; and configure the second number of blocks as MLC blocks. In some embodiments, the one or more processors, individually or in combination, are further configured to: determine a memory capacity resulting from the first number of blocks being configured as SLC blocks and the second number of blocks being configured as MLC blocks; and inform the host of the determined memory capacity. In some embodiments, the first number of blocks are configured as SLC blocks and the second number of blocks are configured as MLC blocks in response to receiving approval from the host of the determined memory capacity. In some embodiments, the one or more processors, individually or in combination, are further configured to: receive a file system update request from the host; and in response to receiving a file system update request from the host, designate the data storage device as having the determining memory capacity. In some embodiments, the first and second numbers are determined using a data structure that associates a plurality of total amounts of data to be written in the memory during the lifetime of the memory with a plurality of capacities of the memory. In some embodiments, the one or more processors, individually or in combination, are further configured to: dynamically populate the data structure based on SLC block size, MLC block size, SLC block endurance, and MLC block endurance. In some embodiments, the request from the host comprises a selection of one of a plurality of options. In some embodiments, the plurality of options is provided to the host by the data storage device via a vendor command. In some embodiments, the one or more processors, individually or in combination, are further configured to use block health metrics in determining the first and second numbers. In some embodiments, the total amount of data is directly expressed in the request from the host. In some embodiments, the total amount of data is indirectly expressed in the request from the host. In some embodiments, the total amount of data is indirectly expressed using a configuration scale. In some embodiments, the memory comprises a three-dimensional memory. In another embodiment, a method is provided that is performed in a data storage device comprising a memory comprising a plurality of memory areas, each memory area being configurable as a single-level cell (SLC) memory area or as a multi-level cell (MLC) memory area. The method comprises: receiving, from a host, an indication of an amount of data to be stored in the memory over a plurality of write cycles; determining an SLC-MLC configuration of the memory to attempt to store the indicated amount of data in the memory over the plurality of write cycles; and configuring the memory according to the determined SLC-MLC configuration. In some embodiments, the SLC-MLC configuration is determined using a data structure that associates a plurality of amounts of data with a plurality of capacities of the memory. In some embodiments, the method further