US-12619529-B2 - Periodic and activity-based memory management

Abstract

Systems, methods, and apparatuses are provided for periodic and activity-based memory management. A memory management bank can be coupled to a memory management block, wherein the memory management bank includes a plurality of memory banks. Each memory bank of the plurality of memory banks includes an activate counter to increment responsive to the memory bank receiving an activate command and circuitry to determine whether a value of the activate counter is equal to or greater than a wear leveling threshold and perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is equal to or greater than the wear leveling threshold.

Inventors

• Bryan D. Kerstetter
• Donald M. Morgan

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20240212

Claims (18)

1. 1 . An apparatus, comprising: a memory management block, wherein the memory management block includes a memory management counter to increment responsive to a memory management bank receiving a memory management command; and the memory management bank coupled to the memory management block, wherein: the memory management bank includes a plurality of memory banks; and each memory bank of the plurality of memory banks includes: an activate counter to increment responsive to the memory bank receiving an activate command; and circuitry to: determine whether a value of the activate counter is equal to or greater than a wear leveling threshold; perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is equal to or greater than the wear leveling threshold; determine whether a value of the memory management counter is equal to or greater than a sense and flip operation threshold; and perform a sense and flip operation on data stored in the memory bank responsive to determining the value of the memory management counter is greater than the sense and flip operation threshold.
2. 2 . The apparatus of claim 1 , wherein an amount of power used for memory management by each memory bank of the plurality of memory banks is proportional to a quantity of activate commands received by the memory bank.
3. 3 . The apparatus of claim 1 , wherein the memory management block is to determine whether a memory operation is performed on data stored in a memory bank of the plurality of memory banks in response to receiving a command.
4. 4 . The apparatus of claim 3 , wherein the memory management block is to determine whether to perform the wear leveling operation on data stored in the memory bank, a sense and flip operation on the data stored in the memory bank, or no operation on the data stored in the memory bank in response to determining the memory operation has been performed on the data.
5. 5 . A method, comprising: determining a value of an activate flag; performing a sense and flip operation on data stored in a memory bank in response to determining the activate flag has a first value; comparing a value of a first counter to a value of a first threshold in response to determining the activate flag has a second value, wherein the first counter is a memory management command counter that increments responsive to the memory bank receiving a memory management command; resetting the value of the first counter in response to determining the value of the first counter is greater than or equal to the value of the first threshold; incrementing the value of the first counter in response to determining the value of the first counter is less than the value of the first threshold; and performing a wear leveling operation on the data stored in the memory in response to determining a value of a second counter is greater than or equal to a value of a second threshold.
6. 6 . The method of claim 5 , wherein the first threshold is sense and flip operation threshold.
7. 7 . The method of claim 5 , wherein the second counter is an activate counter that increments responsive to the memory receiving an activate command.
8. 8 . The method of claim 5 , wherein the second threshold is a wear leveling operation threshold.
9. 9 . The method of claim 5 , further comprising resetting the value of the first counter in response to powering up the memory.
10. 10 . The method of claim 5 further comprising resetting the value of the second counter in response to powering up the memory.
11. 11 . The method of claim 5 , further comprising resetting the value of the activate flag in response to powering up the memory.
12. 12 . The method of claim 5 , further comprising performing a sense and flip operation on the data stored in the memory in response to resetting the value of the first counter.
13. 13 . The method of claim 5 , further comprising refraining from performing the wear leveling operation in response to determining the value of the second counter is less than the value of the second threshold.
14. 14 . A system, comprising: a host; and a memory device coupled to the host, wherein the memory device includes: memory management circuitry, wherein the memory management circuitry includes: a plurality of memory banks; and a memory management block to determine whether to perform a sense and flip operation on data stored in the plurality of memory banks, perform a wear leveling operation on the data stored in the plurality of memory banks, or perform no operation on the data stored in the plurality of memory banks; and wherein each memory bank of the plurality of memory banks includes: a first logic gate to couple the memory bank to the memory management block; circuitry to perform the wear leveling operation; an activate counter to increment responsive to the memory management circuitry receiving an activate command from the host; circuitry to compare a value of the activate counter to a value of a wear leveling threshold; and a second logic gate to couple the memory bank to other memory banks of the plurality of memory banks.
15. 15 . The system of claim 14 , wherein the memory management circuitry includes a third logic gate to couple the memory management block to the first logic gate of each memory bank.
16. 16 . The system of claim 15 , wherein the memory management circuitry is to send a wear leveling operation command to the plurality of memory banks via the third logic gate.
17. 17 . The system of claim 14 , wherein the second logic gate of one of the memory banks of the plurality of memory banks is coupled to ground.
18. 18 . A method, comprising: determining a value of an activate flag; performing a sense and flip operation on data stored in a memory bank in response to determining the activate flag has a first value; setting the value of the activate flag to a second value in response to the memory receiving an activate command; comparing a value of a first counter to a value of a first threshold in response to determining the activate flag has the second value; resetting the value of the first counter in response to determining the value of the first counter is greater than or equal to the value of the first threshold; incrementing the value of the first counter in response to determining the value of the first counter is less than the value of the first threshold; and performing a wear leveling operation on the data stored in the memory in response to determining a value of a second counter is greater than or equal to a value of a second threshold.

Description

PRIORITY INFORMATION This application claims the benefit of U.S. Provisional Application No. 63/447,250, filed on Feb. 21, 2023, the contents of which are incorporated herein by reference. TECHNICAL FIELD Embodiments of the disclosure relate generally to a memory sub-system, and more specifically, relate to periodic and activity-based memory management. BACKGROUND Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), ferroelectric random access memory (FERAM), magnetic random access memory (MRAM), and programmable conductive memory, among others. Memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, and movie players, among other electronic devices. Memory devices can include memory cells that can store data based on the charge level of a storage element or can store data based on their conductivity state. Such memory cells can be programmed to store data corresponding to a target data state by varying the charge level of the storage element or by varying the conductivity level of the storage element. For example, sources of an electrical field or energy, such as positive or negative electrical pulses (e.g., positive or negative voltage or current pulses), can be applied to the memory cell (e.g., to the storage element of the cell) for a particular duration to program the cell to a target data state. A memory cell can be programmed to one of a number of data states. For example, a single level memory cell (SLC) can be programmed to a targeted one of two different data states, which can be represented by the binary units 1 or 0 and can depend on whether the capacitor of the cell is charged or uncharged. As an additional example, some memory cells can be programmed to a targeted one of more than two data states (e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110). Such cells may be referred to as multi state memory cells, multiunit cells, or multilevel cells (MLCs). MLCs can provide higher density memories without increasing the number of memory cells since each cell can represent more than one digit (e.g., more than one data bit). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure. FIG. 2 illustrates periodic and activity-based memory management circuitry in accordance with some embodiments of the present disclosure. FIG. 3 is a flow diagram illustrating a method for periodic and activity-based memory management in accordance with some embodiments of the present disclosure. FIG. 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION The present disclosure includes apparatuses, methods, and systems for periodic and activity-based memory management. An embodiment includes a memory management block and a memory management bank coupled to the memory management block, wherein the memory management bank includes a plurality of memory banks and each memory bank of the plurality of memory banks includes an activate counter to increment responsive to the memory bank receiving an activate command (e.g., from a host or a controller). Each memory bank also includes circuitry to determine whether a value of the activate counter is greater than or equal to a wear leveling threshold (e.g., activity-based memory management threshold) and perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is greater than or equal to the wear leveling threshold. Memory cells can endure a certain amount of memory operations (e.g., activate, program, sense, and/or erase operations) before they wear out (e.g., begin to degrade and/or malfunction). Multiple techniques can be implemented in a memory device to mitigate the effects of such degradation. One such technique is wear leveling. As used herein, the term “wear