US-12619531-B2 - Apparatus and method for distributing and storing write data having different-type entries in plural memory regions

US12619531B2US 12619531 B2US12619531 B2US 12619531B2US-12619531-B2

Abstract

A memory system includes a memory device and a memory controller. The memory device includes a first memory region for storing plural data entries, a second memory region for storing a parity entry associated with the plural data entries, a third memory region for storing at least one partial parity entry corresponding to at least one sub-group, each sub-group including a part of the plural data entries. The memory controller generates a first partial parity entry corresponding to a first sub-group among the at least one sub-group to store the first partial parity entry in the third memory region, generates a second partial parity entry corresponding to a second sub-group among the at least one sub-group, reads the first partial parity entry from the third memory region, and performs a logical operation on the first partial parity entry and the second partial parity entry to generate the parity entry.

Inventors

Hyo Byung HAN
Dong Young Seo
Dong Hyun Cho

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260505
Application Date: 20240422
Priority Date: 20231120

Claims (19)

1 . A memory system comprising: a memory device comprising a first memory region configured to store plural data entries, a second memory region configured to store a parity entry corresponding to the plural data entries, a third memory region configured to store at least one partial parity entry corresponding to at least one sub-group, each sub-group including a part of the plural data entries, wherein each of the first memory region and the second memory region comprises a memory block comprising a plurality of memory cells each configured to store multi-bit data, and the third memory region comprises a memory block comprising a plurality of memory cells each configured to store single-bit data; and a memory controller configured to generate a first partial parity entry corresponding to a first sub-group among the at least one sub-group to store the first partial parity entry in the third memory region, generate a second partial parity entry corresponding to a second sub-group among the at least one sub-group, read the first partial parity entry from the third memory region, and perform a logical operation on the first partial parity entry and the second partial parity entry to generate the parity entry.
2 . The memory system according to claim 1 , wherein the memory controller is configured to invalidate the at least one partial parity entry stored in the third memory region after storing the parity entry in the second memory region.
3 . The memory system according to claim 1 , wherein the first memory region is distributed over a plurality of memory dies, and wherein a physical block address of the third memory region is distinguished from physical block addresses of the first and second memory regions.
4 . The memory system according to claim 1 , wherein the memory controller repeatedly performs an operation for generating and updating the at least one partial parity entry for the at least one sub-group in a preset unit including at least one sub-group, and wherein a size of the partial parity entry stored in the third memory region is identical to a size of the parity entry stored in the second memory region.
5 . The memory system according to claim 1 , wherein the memory controller reads the first partial parity entry from the third memory region when a number of first partial parity entries is 1/N of a total number of sub-groups associated with the plural data entries, where N is a natural number of 2 or more.
6 . The memory system according to claim 1 , wherein the logical operation is an exclusive OR (XOR) operation.
7 . The memory system according to claim 1 , wherein the memory controller comprises parity generating circuitry comprising: a calculation circuit configured to perform the logical operation; and a buffer coupled to the calculation circuit, the buffer having a size corresponding to a size of the sub-group.
8 . The memory system according to claim 1 , wherein the third memory region is adjacent to the first memory region.
9 . The memory system according to claim 1 , wherein the third memory region is a dedicated space for storing the partial parity entry.
10 . A memory controller coupled to a memory device, wherein the memory controller is configured to: divide plural data entries into plural sub-groups to be stored in a first memory region of the memory device, wherein the first memory region comprises first memory cells, each first memory cell configured to store multi-bit data; generate a first partial parity entry corresponding to a first sub-group among the plural sub-groups to store the first partial parity entry in a third memory region of the memory device, wherein the third memory region comprises third memory cells, each third memory cell configured to store single-bit data; generate a second partial parity entry corresponding to a second sub-group among the plural sub-groups; read the first partial parity entry stored in the third memory region of the memory device; perform a logical operation on the first partial parity entry and the second partial parity entry to generate a parity entry associated with the plural data entries; and store the parity entry in a second memory region of the memory device, wherein the second memory region comprises second memory cells, each second memory cell configured to store multi-bit data.
11 . The memory controller according to claim 10 , wherein the memory controller is configured to invalidate the first partial parity entry and the second partial parity entry after storing the parity entry in the memory device.
12 . The memory controller according to claim 10 , wherein the first partial parity entry, the second partial parity entry, and the parity entry are generated by parity generating circuitry included in the memory controller, and wherein the parity generating circuitry comprises a buffer having a size corresponding to a size of each of the plural sub-groups.
13 . The memory controller according to claim 12 , wherein the sub-group has a size corresponding to K number of pages set in the memory device, where K is a natural number.
14 . The memory controller according to claim 10 , wherein the memory controller repeatedly performs an operation for generating and updating partial parity entries corresponding to the plural sub-groups in a preset unit including at least one sub-group, and wherein a size of each partial parity entry stored in the third memory region is identical to as a size of the parity entry stored in the second memory region.
15 . The memory controller according to claim 10 , wherein the memory controller reads the first partial parity entry from the third memory region when a number of first partial parity entries is 1/N of a total number of sub-groups associated with the plural data entries, where N is a natural number of 2 or more.
16 . A memory system comprising: plural memory regions comprising plural memory dies, plural memory planes, or plural memory blocks in which plural data entries and a parity entry associated with the plural data entries are distributed and stored to restore an uncorrectable error correction code (UECC); and a memory controller configured to divide the plural data entries into plural sub-groups to be stored in a first memory region of the plural memory regions, generate a first partial parity entry corresponding to a first sub-group among the plural sub-groups to store the first partial parity entry in a third memory region of the plural memory regions, generate a second partial parity entry corresponding to a second sub-group among the plural sub-groups, read the first partial parity entry stored in the third memory region of the plural memory regions, and perform a logical operation on the first partial parity entry and the second partial parity entry to generate the parity entry and store the parity entry in a second memory region of the plural memory regions, wherein each of the first memory region and the second memory region comprises first memory cells, each first memory cell configured to store multi-bit data, and wherein the third memory region comprises third memory cells, each third memory cell configured to store single-bit data.
17 . The memory system according to claim 16 , wherein the plural memory regions are coupled via plural channels to the memory controller.
18 . The memory system according to claim 16 , wherein each of the plural sub-groups comprises data stored in memory cells indicated by a same word line address and a same cell string address in the plural memory regions.
19 . The memory system according to claim 16 , wherein the memory controller is configured to invalidate the first partial parity entry and the second partial parity entry after storing the parity entry in the memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0160999 filed on Nov. 20, 2023, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD One or more embodiments of the present disclosure described herein relate to a memory system or a memory device, and an operation method thereof, and more particularly, to an apparatus and a method for distributing and programming write data entries in plural regions of the memory device. BACKGROUND A data processing system includes a memory system or a data storage device. The data processing system can be developed to store more voluminous data in the data storage device, store data in the data storage device faster, and read data stored in the data storage device faster. The memory system or the data storage device can include non-volatile memory cells and/or volatile memory cells for storing data. To improve data safety, data can be distributed and stored in plural regions of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the figures. FIG. 1 is a diagram illustrating a configuration of a data storage apparatus according to an embodiment of the present disclosure. FIG. 2 is a diagram for describing a method for operating a memory system according to an embodiment of the present disclosure. FIG. 3 is a diagram for describing operations of a first part in a procedure performed within a memory system according to another embodiment of the present disclosure. FIG. 4 is a diagram for describing operations of a second part in the procedure performed within a memory system according to another embodiment of the present disclosure. FIG. 5 is a diagram for describing operations of a third part in the procedure performed within a memory system according to another embodiment of the present disclosure. FIG. 6 is a diagram illustrating a detailed configuration of parity generation engine shown in FIG. 1, according to another embodiment of the present disclosure. FIG. 7 is a diagram illustrating a configuration of redundant array of independent disks (RAID). FIG. 8 is a diagram for describing how to distribute and store plural data entries in a memory device, according to an embodiment of the present disclosure. FIG. 9 is a diagram illustrating a configuration of a memory system according to another embodiment of the present disclosure. FIG. 10 is a diagram illustrating a configuration of a memory system according to another embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments of the present disclosure are described below with reference to the accompanying drawings. Elements and features of this disclosure, however, may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments. In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiment,” and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments. In this disclosure, the terms “comprise,” “comprising,” “include,” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. The terms in a claim do not foreclose the apparatus from including additional components e.g., an interface unit, circuitry, etc. In this disclosure, various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the blocks/units/circuits/components include structure (e.g., circuitry) that performs one or more tasks during operation. As such, the block/unit/circuit/component can be said to be configured to perform the task even when the specified block/unit/circuit/component is not currently operational, e.g., is not turned on nor activated. Examples of block/unit/circuit/component used with the “configured to” language include hardware, circuits, memory storing program instructions executable to implement the operation, etc. Additionally, “configured to” can include a generic structure, e.g., generic circuitry, that is manipulated by software and/or firmware, e.g., an FPGA or a general-purpose processor executing software to operate in a manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturin