US-12619533-B1 - Data storage device and method for non-balanced mapping for variable read resolution

US12619533B1US 12619533 B1US12619533 B1US 12619533B1US-12619533-B1

Abstract

Data is often stored in a multi-level memory (e.g., a quad-level cell (QLC)) using a mapping that balances the bit error rate among the various pages in the memory. The number of sense operations needed to read each page is also relatively balanced. The data storage device presented herein can decide to store data using a non-balanced mapping if there is a desire to later read a low-resolution version of the data. With a non-balanced mapping, fewer sense operations are needed to read the lower page of data, which contains the low-resolution version of the data. Other pages can be read if a higher-resolution version of the data is desired, and techniques can be used to mitigate the higher bit error rate that may be encountered in those other pages because of use of the non-balanced mapping.

Inventors

Eran Sharon
Ariel Navon

Assignees

SanDisk Technologies, Inc.

Dates

Publication Date: 20260505
Application Date: 20250123

Claims (20)

1 . A data storage device comprising: a memory comprising multi-level memory cells; and one or more processors, individually or in combination, configured to: determine whether there is a need for providing a low-resolution version of data; in response to determining that there is not a need for providing a low-resolution version of the data, store the data in the memory using a first mapping; and in response to determining that there is a need for providing a low-resolution version of the data, store the data in the memory using a second mapping, wherein reading only a lower page of the data provides the low-resolution version of the data, and wherein fewer memory sense operations are needed to read the lower page when the data is stored using the second mapping than when the data is stored using the first mapping.
2 . The data storage device of claim 1 , wherein the first mapping comprises a 4-4-3-4 mapping and the second mapping comprises a 1-2-4-8 mapping.
3 . The data storage device of claim 1 , wherein the first mapping comprises a bit error rate (BER) balanced mapping and the second mapping comprises a non-BER-balanced mapping.
4 . The data storage device of claim 1 , wherein the determining is performed in response to the data being received from a host.
5 . The data storage device of claim 1 , wherein the determining is performed in response to re-mapping the data, which was previously stored in the memory using a different mapping.
6 . The data storage device of claim 1 , wherein most-significant bits of the data are stored in the lower page.
7 . The data storage device of claim 1 , wherein the low-resolution version of the data comprises a low-resolution version of a parameter of a machine learning model.
8 . The data storage device of claim 1 , wherein the low-resolution version of the data comprises a low-resolution version of an image.
9 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.
10 . In a data storage device comprising multi-level memory cells, a method comprising: determining whether data is designated for reading with dynamic read resolution; and in response to determining that the data is designated for reading with dynamic read resolution, storing the data in the memory using a non-BER (bit-error-rate) balanced mapping, wherein fewer memory sense operations are needed to read page(s) of the data for a low-resolution read when the data is stored using the non-BER-balanced mapping instead of a BER-balanced mapping.
11 . The method of claim 10 , further comprising: performing an operation to mitigate non-balanced BER caused by using the non-BER-balanced mapping.
12 . The method of claim 11 , further comprising: reading a higher-resolution of the data by reading more pages of the data from the memory.
13 . The method of claim 10 , wherein the data comprises an image.
14 . The method of claim 10 , wherein the data comprises a parameter of a machine-learning model.
15 . The method of claim 10 , wherein the determining is performed in response to the data being received from a host.
16 . The method of claim 10 , wherein the determining is performed in response re-mapping the data, which was previously stored in the memory using a different mapping.
17 . The method of claim 10 , wherein the data is explicitly designated for reading with dynamic read resolution by a host.
18 . The method of claim 10 , wherein the data is implicitly designated for reading with dynamic read resolution by a host.
19 . The method of claim 10 , wherein the BER balanced mapping comprises a 4-4-3-4 mapping and the non-BER balanced mapping comprises a 1-2-4-8 mapping.
20 . A data storage device comprising: a memory comprising multi-level memory cells; and means for: selecting a mapping from a plurality of mappings based on whether the data is designated for variable read resolution; and writing the data in the memory using the selected mapping.

Description

BACKGROUND A memory of a data storage device can contain memory cells that store more than one bit of data per cell. For example, a quad-level cell (QLC) can store four bits of data. The four bits of data in a QLC cell belong to four pages (a lower page, a middle page, an upper page, and a top page), and a mapping can be used to store data in the various logical pages. For example, using a 4-4-3-4 mapping, the data is written into a QLC cell in such a way that the lower, middle, and top pages can be read by sensing the cell voltage in four steps, whereas the upper page can be read by sensing the cell voltage in three steps. With this mapping, the number of transitions between adjacent states is divided approximately equally between the logical pages. Because the bits representative of adjacent states differs from each other only by one bit, this mapping can be used to balance the bit error rate (BER) among the pages. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram of a data storage device of an embodiment. FIG. 1B is a block diagram illustrating a storage module of an embodiment. FIG. 1C is a block diagram illustrating a hierarchical storage system of an embodiment. FIG. 2A is a block diagram illustrating components of the controller of the data storage device illustrated in FIG. 1A according to an embodiment. FIG. 2B is a block diagram illustrating components of the data storage device illustrated in FIG. 1A according to an embodiment. FIG. 3 is a block diagram of a host and a data storage device of an embodiment. FIG. 4 is an illustration of a 4-3-4-4 bit error rate (BER) balanced mapping of an embodiment. FIG. 5 is an illustration of a 1-2-4-8 non-balanced mapping of an embodiment. FIG. 6 is a flow chart of a method of an embodiment for writing data received from a host. FIG. 7 is a flow chart of a method of an embodiment for re-mapping previously-written data. DETAILED DESCRIPTION The following embodiments generally relate to a data storage device and method for non-balanced mapping for variable read resolution. In one embodiment, a data storage device is provided comprising a memory comprising multi-level memory cells and one or more processors. The one or more processors, individually or in combination, are configured to: determine whether there is a need for providing a low-resolution version of data; in response to determining that there is not a need for providing a low-resolution version of the data, store the data in the memory using a first mapping; and in response to determining that there is a need for providing a low-resolution version of the data, store the data in the memory using a second mapping, wherein reading only a lower page of the data provides the low-resolution version of the data, and wherein fewer memory sense operations are needed to read the lower page when the data is stored using the second mapping than when the data is stored using the first mapping. In another embodiment, a method is provided that is performed in a data storage device comprising multi-level memory cells. The method comprises: determining whether data is designated for reading with dynamic read resolution; and in response to determining that the data is designated for reading with dynamic read resolution, storing the data in the memory using a non-BER (bit-error-rate) balanced mapping, wherein fewer memory sense operations are needed to read a lower page of the data when the data is stored using the non-BER-balanced mapping instead of a BER-balanced mapping. In yet another embodiment, a data storage device is provided comprising: a memory comprising multi-level memory cells; and means for: selecting a mapping from a plurality of mappings based on whether the data is designated for variable read resolution; and writing the data in the memory using the selected mapping. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings. Embodiments The following embodiments relate to a data storage device (DSD). As used herein, a “data storage device” refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, hybrid drives, etc. Details of example DSDs are provided below. Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in FIGS. 1A-1C. It should be noted that these are merely examples and that other implementations can be used. FIG. 1A is a block diagram illustrating the data storage device 100 according to an embodiment. Referring to FIG. 1A, the data storage device 100 in this example includes a controller 102 coupled with a non-volatile memory that may be made up of one or more non-volatile memory die 104. As used herein, the term die refers to the collection of non-volatile memory cells, and associated