US-12619534-B2 - Interconnect based address mapping for improved reliability

Abstract

Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

Inventors

• Taeksang Song
• Steven C. Woo
• Torsten Partsch

Assignees

• RAMBUS INC.

Dates

Publication Date

20260505

Application Date

20240805

Claims (19)

1. 1 . A controller, comprising: a module command/address (CA) interface to transmit a first plurality of CA signals to a memory module, the memory module comprising: first signal interconnections operatively coupling the module CA interface and a first device CA interface of a first memory device, the first signal interconnections implementing at least a first permutation function of the first plurality of CA signals between the module CA interface and the first device CA interface; second signal interconnections operatively coupling the module CA interface and a second device CA interface of a second memory device, the second signal interconnections implementing a second permutation function of the first plurality of CA signals between the module CA interface and the second device CA interface; and the controller further comprising circuitry to place the first memory device in a first operating mode that undoes the first permutation function for signals received via the first device CA interface and to place the second memory device in a second operating mode that undoes the second permutation function for signals received via the second CA interface.
2. 2 . The controller of claim 1 , further comprising: circuitry to transmit a training sequence via the module CA interface.
3. 3 . The controller of claim 2 , wherein the controller is to, based on responses by the first memory device the training sequence, determine that the first memory device is receiving addresses that have been transformed by at least the first permutation function.
4. 4 . The controller of claim 3 , wherein the controller is to, based on responses by the second memory device the training sequence, determine that the second memory device is receiving addresses that have been transformed by at least the second permutation function.
5. 5 . The controller of claim 4 , wherein the controller is to determine, based on the first permutation function, a third permutation function that undoes the first permutation function.
6. 6 . The controller of claim 5 , wherein the controller is to determine, based on the second permutation function, a fourth permutation function that undoes the second permutation function.
7. 7 . A method of operating a controller, comprising: transmitting, by the controller and via a module command/address (CA) interface of a memory module, a first row address composed of a first plurality of address bits, the first row address being transformed, by the memory module, into a second row address composed of a first permutation of the first plurality of address bits and a third row address composed of a second permutation of the first plurality of address bits, the second row address being received, by a first device CA interface of a first dynamic random access memory (DRAM) device on the memory module that includes a first memory array, the third row address being received, by a second device CA interface of a second DRAM device on the memory module that includes a second memory array; based on the second row address and based on the first DRAM device being in a first operating mode, accessing, by the controller, a first row in the first memory array that has a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address; based on the third row address and based on the second DRAM device being in the first operating mode, accessing, by the controller, a second row in the second memory array that has a second internal row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, wherein a first external row address received via the module CA interface that maps to the first internal neighboring row address and a second external row address received via the module CA interface that maps to the second internal neighboring row address are not equal; transmitting, by the controller and via the module CA interface, a mode setting command to place the first DRAM device in a second operating mode and the second DRAM device in a third operating mode; and transmitting, by the controller and via the module CA interface of the memory module, a fourth row address composed of a second plurality of address bits that is received, by the first device CA interface of the first DRAM device, a fifth row address composed of the first permutation of the second plurality of address bits, the fifth row address to, based on the first DRAM device being in the second operating mode, be translated, by the first DRAM device into the fourth row address.
8. 8 . The method of claim 7 , wherein a first interconnect network on the memory module maps the first row address to the second row address, and a second interconnect network on the memory module maps the first row address to the third row address.
9. 9 . The method of claim 7 , wherein the first permutation of the first plurality of address bits is a first circular shift of the first row address by a first number of bits, and the second permutation of the first plurality of address bits is a second circular shift of the first row address by a second number of bits, wherein the first number of bits and the second number of bits produce circularly shifted outputs that are not equivalent.
10. 10 . The method of claim 7 , further comprising: transmitting a training sequence via the module CA interface; based on responses by the first DRAM device to the training sequence, determining, by the controller, a third permutation function that reverses the first permutation; and based on responses by the first DRAM device to the training sequence, determining, by the controller, a fourth permutation function that reverses the second permutation.
11. 11 . The method of claim 10 , further comprising: by the controller, using the third permutation function to determine the second row address.
12. 12 . A controller, comprising: a module command/address (CA) interface to transmit a first row address to a memory module, the memory module comprising: a first memory device including a first memory array and a first memory device CA interface, the first memory device to receive, via the first memory device CA interface, a second row address generated from the first row address by the memory module using a first mapping, the first mapping comprising a first permutation function relating signals received via the module CA interface to signal provided to the first device CA interface, the second row address to access a first row in the first memory array having a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address, the first memory device including circuitry to, when in a first operating mode, translate the second row address to the first row address; and a second memory device including a second memory array and a second device command/address interface, the second memory device to receive, via the second device command/address interface, a third row address generated from the first row address using a second mapping that comprises a second permutation function relating signals received via the module CA interface to signals provided to the second device command/address interface, the third row address to access a second row in the second memory array having a second internal neighboring row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, wherein the first internal neighboring row address and the second internal neighboring row address do not address a same row.
13. 13 . The controller of claim 12 , wherein the controller is to transmit, to the module CA interface, a first command to place the first memory device in the first operating mode.
14. 14 . The controller of claim 13 , wherein the second memory device includes circuitry to, when in a second operating mode, translate the third row address to the first row address.
15. 15 . The controller of claim 14 , wherein controller is to transmit, to the module CA interface, a second command to place the second memory device in the second operating mode.
16. 16 . The controller of claim 12 , wherein the first mapping comprises at least one of an inversion of a first signal between the module CA interface and the first device CA interface, and a permutation of the signals of the module CA interface made according to a permutation function.
17. 17 . The controller of claim 12 , wherein the controller is to, based on responses by the first memory device to a training sequence transmitted by the controller via the module CA interface, determine a third permutation function that reverses the first permutation function.
18. 18 . The controller of claim 17 , wherein the controller is to, based on responses by the second memory device to the training sequence transmitted by the controller via the module CA interface, determine a fourth permutation function that reverses the second permutation function.
19. 19 . The controller of claim 18 , wherein the first permutation function circularly shifts the first row address by a first number of bits when mapping the first row address to the second row address and the second permutation function circularly shifts the first row address by a second number of bits when mapping the first row address to the third row address.

Description

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1B are a block diagrams illustrating an example memory system. FIG. 2 is a block diagram illustrating an example buffered memory module system. FIG. 3 is a flowchart illustrating a method of operating a memory module. FIG. 4 is a flowchart illustrating a method of determining a transformation to reverse an interconnect based address transformation. FIG. 5 is a flowchart illustrating a method of determining address transformations. FIG. 6 is a flowchart illustrating a method of reversing address transformations. FIG. 7 is a flowchart illustrating a method of transmitting addresses. FIG. 8 is a block diagram of a processing system. DETAILED DESCRIPTION OF THE EMBODIMENTS Repeated row activations of the same row in a memory device (e.g., dynamic random access memory—DRAM), whether malicious or accidental, may cause cells in the neighborhood of the repeatedly activated row to lose a stored value. This effect on storage reliability has been termed “row hammer.” Row hammer, when applied to the multiple, parallel, memory device accesses that occur with memory modules, can cause multiple errors across multiple devices on the module. When many errors occur across multiple memory devices, error detection and correction schemes such as Chipkill (a.k.a., “single device data correct”—SDDC) and SSDC/DSDD (i.e., “single symbol data correct”—SSDC with “double symbol data detect”—DSDD) may be overwhelmed by the number and distribution of errors and thereby unable to correct these row hammer caused errors (or in some cases, detect the errors). In an embodiment, row addressing received by a module is mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device (i.e., the addresses received via the command/address interface of a given device) to respective internal row addresses (i.e., an ordinal row number of the row in the respective device's memory core—for example, if the rows of the array are addressed in order, from top to bottom, the internal row address that selects a row from top to bottom are 0, 1, 2, 3, . . . ) ensure that each set of neighboring rows for a given row address received by the module is different for each memory device in a module's rank, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device during a column access (Read or Write). By confining the row hammer errors to a single memory device per column access, the row hammer errors are correctible using a SDDC scheme. In an embodiment, the module row address to device row address mappings comprise different permutations of the module row address bits for each memory device on the module. The descriptions and embodiments disclosed herein are made primarily with references to DRAM devices and DRAM memory arrays. This, however, should be understood to be a first example where, due at least to the widespread adoption of DRAM technology, “row-hammer” has been observed and studied. It should be understood that other memory technologies that may be susceptible to “row-hammer” and therefore may also benefit from the methods and/or apparatus described herein. These memory technologies include, but are not limited to static random access memory (SRAM), non-volatile memory (such as flash), conductive bridging random access memory (CBRAM—a.k.a., programmable metallization cell—PMC), resistive random access memory (a.k.a., RRAM or ReRAM), magnetoresistive random-access memory (MRAM), Spin-Torque Transfer (STT-MRAM), phase change memory (PCM), and the like, and/or combinations thereof. Accordingly, it should be understood that in the disclosures and/or descriptions given herein, these aforementioned technologies may be substituted for, included with, and/or encompassed within, the references to DRAM, DRAM devices, and/or DRAM arrays made herein. FIGS. 1A-1B are a block diagrams illustrating an example memory system. In FIGS. 1A-1B, memory system 100 comprises controller 120 and memory module 150. Controller 120 includes interfaces operatively coupled with memory module 150 (e.g., memory channel interfaces comprising command/address and data interfaces) and reliability, availability, and serviceability (RAS) circuitry 123 (e.g., error detect and correct—EDC, error correcting code—ECC, chipkill SDDC, memory scrubbing, etc. circuitry). Memory module 150 includes memory devices 110a-110c, command/address (CA) interface 151, data (DQ) interfaces 152a-152c, and address mapping interconnect 155a-155c. Memory devices 110a-110c, respectively, include memory device CA interfaces 111a-111c, DQ interfaces 112a-112c, control circuitry 113a-113c, memory