US-12619535-B2 - Invalidate-write hazard detection

US12619535B2US 12619535 B2US12619535 B2US 12619535B2US-12619535-B2

Abstract

An apparatus comprises invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation; cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry.

Inventors

Mark Underwood
Ole Henrik JAHREN
Harsh Ashok GUGALE

Assignees

ARM LIMITED

Dates

Publication Date: 20260505
Application Date: 20240607

Claims (20)

1 . An apparatus comprising: invalidation range tracking circuitry configured to track at least one invalidation target address range specified as a target for cache invalidation by at least one discard command; cache invalidation circuitry configured to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry configured to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry in response to the at least one discard command occurring before the memory write request.
2 . The apparatus according to claim 1 , in which, in response to detecting an invalidate-write hazard for a given memory write request which specifies a write target address in a given invalidation target address range tracked by the invalidation range tracking circuitry, when at least one cache invalidation request has already been issued for the given invalidation target address range: the invalidation-write hazard detection circuitry is configured to prevent the given memory write request being serviced until each cache invalidation request previously issued for the given invalidation target address range has been acknowledged as being guaranteed to complete.
3 . The apparatus according to claim 1 , comprising memory permissions checking circuitry to perform a permissions check for a memory access request based on permissions data associated with a target address of the memory access request, in which, in response to detecting an invalidate-write hazard for a given memory write request, the invalidation-write hazard detection circuitry is configured to prevent the memory permissions checking circuitry indicating that the permissions check for the given memory write request is successful until the invalidate-write hazard is resolved.
4 . The apparatus according to claim 1 , comprising memory permissions checking circuitry to perform a permissions check for a memory access request based on permissions data associated with a target address of the memory access request, in which in response to a permissions check request received by the memory permissions checking circuitry specifying a given write target address for which the permissions check is requested corresponding to a given memory write request, the invalidate-write hazard detection circuitry is configured to compare the given write target address specified by the permissions check request with the at least one invalidation target address range to determine whether an invalidate-write hazard is detected for the given memory write request.
5 . The apparatus according to claim 1 , comprising memory permissions checking circuitry to perform a permissions check for a memory access request based on permissions data associated with a target address of the memory access request, in which the memory permissions checking circuitry comprises memory management circuitry to obtain translation table data corresponding to the target address of the memory access request, the translation table data specifying the permissions data and address translation mapping information.
6 . The apparatus according to claim 5 , comprising at least one translation lookaside buffer to cache address translation data, and to trigger issuing of a translation request to the memory management circuitry in response to detecting a miss in the at least one translation lookaside buffer; wherein in response to allocation of a new invalidation target address range to be tracked by the invalidation range tracking circuitry, the invalidation range tracking circuitry is configured to trigger the at least one translation lookaside buffer to invalidate or update translation lookaside buffer entries corresponding to the new invalidation target address range to indicate that a subsequent memory write request specifying an address corresponding to the new invalidation target address range should cause the translation request to be issued to the memory management circuitry.
7 . The apparatus according to claim 1 , in which, in response to a software command specifying invalidation target range identifying information, the invalidation range tracking circuitry is configured to allocate, as a new invalidation target address range, a range of addresses identified by the invalidation target range identifying information.
8 . The apparatus according to claim 1 , in which each invalidation target address range tracked by the invalidation range tracking circuitry is specified as a range of virtual addresses or a range of intermediate addresses.
9 . The apparatus according to claim 1 , in which, following allocation of a given invalidation target address range to be tracked by the invalidation range tracking circuitry, the cache invalidation circuitry is configured to start, in response to detection of completion of a consumer task that consumes data from addresses in the given invalidation target address range, generation of cache invalidation requests requesting invalidation of cache entries corresponding to addresses in the given invalidation target address range.
10 . The apparatus according to claim 1 , in which the invalidation range tracking circuitry is configured to maintain, for each invalidation target address range tracked by the invalidation range tracking circuitry: an invalidating indication indicative of whether the cache invalidation circuitry has started generation of cache invalidation requests corresponding to that invalidation target address range; and a hazard indication indicative of whether at least one invalidate-write hazard has been detected for a memory write request specifying a target write address in that invalidation target address range.
11 . The apparatus according to claim 1 , in which, in response to detecting an invalidate-write hazard for a given memory write request specifying a write target address in a given invalidation target address range tracked by the invalidation range tracking circuitry, the invalidate-write hazard being detected before any cache invalidation requests have been generated by the cache invalidation circuitry for the given invalidation target address range: the invalidate-write hazard detection circuitry is configured to perform an invalidation cancelling action to prevent the cache invalidation circuitry generating cache invalidation requests for the given invalidation target address range, and allow the given memory write request to proceed.
12 . The apparatus according to claim 1 , in which, in response to detecting an invalidate-write hazard for a given memory write request specifying a write target address in a given invalidation target address range tracked by the invalidation range tracking circuitry, the invalidate-write hazard being detected after at least one cache invalidation request has already been generated by the cache invalidation circuitry for the given invalidation target address range: the invalidate-write hazard detection circuitry is configured to: control the cache invalidation circuitry to halt generation of further cache invalidation requests corresponding to the given invalidation target address range; and prevent the given memory write request being serviced until any previously generated cache invalidation request has been acknowledged as being guaranteed to complete.
13 . The apparatus according to claim 1 , in which in response to completion of a cache invalidation process corresponding to a given invalidation target address range tracked by the invalidation range tracking circuitry without any invalidate-write hazard being detected, or halting or cancellation of the cache invalidation process in response to an invalidate-write hazard being detected, the invalidation range tracking circuitry is configured to invalidate a tracking entry used by the invalidation range tracking circuitry to track the given invalidation target address range.
14 . The apparatus according to claim 1 , in which the invalidate-write hazard detection circuitry is configured to detect invalidate-write hazards for memory write requests issued by a given memory access initiator; in which the given memory access initiator comprises a graphics processing unit (GPU).
15 . The apparatus according to claim 1 , in which the invalidate-write hazard detection circuitry is configured to detect invalidate-write hazards for memory write requests issued by a given memory access initiator; and the cache invalidation circuitry is configured to generate cache invalidation requests capable of causing invalidation of cache entries from a system cache shared between the given memory access initiator and at least one central processing unit (CPU).
16 . A system comprising: the apparatus of claim 1 , implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.
17 . A chip-containing product comprising the system of claim 16 , wherein the system is assembled on a further board with at least one other product component.
18 . The apparatus according to claim 1 , wherein the at least one discard command indicates that cache entries corresponding to the at least one invalidation target address range are discardable, even if the cache entries contain data which is dirty.
19 . A non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus comprising: invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation by at least one discard command; cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry in response to the at least one discard command occurring before the memory write request.
20 . A method comprising: tracking, using invalidation range tracking circuitry, at least one invalidation target address range specified as a target for cache invalidation by at least one discard command; requesting invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and detecting invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry in response to the at least one discard command occurring before the memory write request.

Description

BACKGROUND Technical Field The present technique relates to the field of data processing. Technical Background A data processing system may have a cache for caching data from memory for faster access. Cache capacity may be limited and so when new data is to be allocated into the cache, other data may need to be evicted to make way for the new data. If the evicted data is dirty (has been modified relative to the corresponding data in memory), eviction of the dirty data may trigger a writeback of the dirty data back to the memory. SUMMARY At least some examples of the present technique provide an apparatus comprising: invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation;cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; andinvalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry. At least some examples of the present technique provide a system comprising: the apparatus described above, implemented in at least one packaged chip; at least one system component; anda board, wherein the at least one packaged chip and the at least one system component are assembled on the board. At least some examples of the present technique provide a chip-containing product comprising the system described above, wherein the system is assembled on a further board with at least one other product component. At least some examples of the present technique provide a non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus comprising: invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation;cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; andinvalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry. At least some examples of the present technique provide a method comprising: tracking, using invalidation range tracking circuitry, at least one invalidation target address range specified as a target for cache invalidation;requesting invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; anddetecting invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry. Further aspects, features and advantages of the present technique will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a data processing apparatus; FIG. 2 illustrates an example of a graphics processing unit (GPU) comprising a discard manager; FIG. 3 illustrates an example of a discard manager comprising invalidation range tracking circuitry, cache invalidation circuitry and invalidate-write hazard detection circuitry; FIG. 4 illustrates an example of tracking entries of the invalidation range tracking circuitry; FIG. 5 illustrates steps for detection of invalidate-write hazards; FIG. 6 illustrates steps for allocation of a new invalidation target address range; FIG. 7 illustrates steps for invalidation of an entry of the invalidation range tracking circuitry; FIG. 8 illustrates steps for detecting, and responding to detection of, an invalidate-write hazard; and FIG. 9 illustrates a system and a chip-containing product. DESCRIPTION OF EXAMPLES There can be some processing workloads for which dirty cached data associated with a given range of addresses is temporarily needed for a time, but then will never be used again once processing has progressed beyond a certain point. For example, the dirty cached data could correspond to results of an intermediate phase of processing (e.g. a given render pass applied to an image frame in a graphics processing workload) which may not be needed again once it has been consumed by the next phase of processing (e.g. a subsequent render pass on the same frame). However, if the data remains dirty in the cache beyond the point at which the consumer processing is done with it, there can be a power a