US-12619536-B2 - Memory controller, memory system for dataset management handling, method, and storage medium thereof

Abstract

In certain aspects, a memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide a deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones which are classified into one or more aligned zones, respectively. The deallocation accelerator is operatively coupled to the data classification accelerator, and configured to update a dataset management (DSM) bitmap based on the one or more aligned zones. The mapping table accelerator is operatively coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to, responsive to the updating of the DSM bitmap, generate a response indicating that the deallocated logical range is processed.

Inventors

• Weilin Liu

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260505

Application Date

20230821

Claims (20)

1. 1 . A memory controller, comprising: a data classification accelerator configured to receive a command indicative of a deallocated logical range from a host and divide the deallocated logical range into a set of deallocation zones, wherein the set of deallocation zones comprises one or more first deallocation zones which are classified into one or more aligned zones, respectively, and one or more second deallocation zones which are classified into one or more unaligned zones, respectively; a deallocation accelerator operatively coupled to the data classification accelerator, and configured to update one or more bits of a dataset management (DSM) bitmap that correspond to the one or more aligned zones, respectively, from a first bit value to a second bit value to indicate that the one or more aligned zones are to be deallocated; and a mapping table accelerator operatively coupled to the data classification accelerator and the deallocation accelerator, and configured to: update a logical-to-physical (L2P) mapping table based on the one or more unaligned zones to deallocate the one or more unaligned zones; responsive to the updating of the one or more bits of the DSM bitmap and the deallocating of the one or more unaligned zones, generate a response before the one or more aligned zones are deallocated, the response indicating that the deallocated logical range is processed; and send the response to the host after the one or more unaligned zones are deallocated but before the one or more aligned zones are deallocated.
2. 2 . The memory controller of claim 1 , wherein the mapping table accelerator is further configured to update the L2P mapping table based on the DSM bitmap.
3. 3 . The memory controller of claim 2 , wherein to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator is further configured to: identify the one or more aligned zones based on the one or more bits of the DSM bitmap; and update the L2P mapping table based on the one or more aligned zones.
4. 4 . The memory controller of claim 3 , wherein to update the L2P mapping table based on the one or more aligned zones, the mapping table accelerator is further configured to: identify a first list of logical addresses within the one or more aligned zones; and invalidate the first list of logical addresses in the L2P mapping table.
5. 5 . The memory controller of claim 1 , wherein to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator is further configured to: identify a second list of logical addresses within the one or more unaligned zones; and invalidate the second list of logical addresses in the L2P mapping table.
6. 6 . The memory controller of claim 1 , wherein the data classification accelerator is configured to divide the deallocated logical range into the set of deallocation zones based on a zone division of a logical space of a non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical range matches the zone division of the logical space of the non-volatile memory device.
7. 7 . The memory controller of claim 6 , wherein: the logical space of the non-volatile memory device is divided into a plurality of logical zones; the one or more first deallocation zones are equal to one or more first logical zones from the plurality of logical zones, respectively, such that the one or more first deallocation zones are classified into the one or more aligned zones which are aligned with the one or more first logical zones, respectively; and the one or more second deallocation zones are smaller than one or more second logical zones from the plurality of logical zones, respectively, such that the one or more second deallocation zones are classified into the one or more unaligned zones that are unaligned with the one or more second logical zones, respectively.
8. 8 . The memory controller of claim 6 , wherein the non-volatile memory device comprises NAND Flash memory.
9. 9 . A memory system, comprising: a non-volatile memory device; and a memory controller operatively coupled to the non-volatile memory device and configured to control the non-volatile memory device, the memory controller comprising: a data classification accelerator configured to receive a command indicative of a deallocated logical range from a host and divide the deallocated logical range into a set of deallocation zones, wherein the set of deallocation zones comprises one or more first deallocation zones which are classified into one or more aligned zones, respectively, and one or more second deallocation zones which are classified into one or more unaligned zones, respectively; a deallocation accelerator operatively coupled to the data classification accelerator, and configured to update one or more bits of a dataset management (DSM) bitmap that correspond to the one or more aligned zones, respectively, from a first bit value to a second bit value to indicate that the one or more aligned zones are to be deallocated; and a mapping table accelerator operatively coupled to the data classification accelerator and the deallocation accelerator, and configured to: update a logical-to-physical (L2P) mapping table based on the one or more unaligned zones to deallocate the one or more unaligned zones; responsive to the updating of the one or more bits of the DSM bitmap and the deallocating of the one or more unaligned zones, generate a response before the one or more aligned zones are deallocated, the response indicating that the deallocated logical range is processed; and send the response to the host after the one or more unaligned zones are deallocated but before the one or more aligned zones are deallocated.
10. 10 . The memory system of claim 9 , wherein the mapping table accelerator is further configured to update the L2P mapping table based on the DSM bitmap.
11. 11 . The memory system of claim 10 , wherein to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator is further configured to: identify the one or more aligned zones based on the one or more bits of the DSM bitmap; and update the L2P mapping table based on the one or more aligned zones.
12. 12 . The memory system of claim 11 , wherein to update the L2P mapping table based on the one or more aligned zones, the mapping table accelerator is further configured to: identify a first list of logical addresses within the one or more aligned zones; and invalidate the first list of logical addresses in the L2P mapping table.
13. 13 . The memory system of claim 9 , wherein to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator is further configured to: identify a second list of logical addresses within the one or more unaligned zones; and invalidate the second list of logical addresses in the L2P mapping table.
14. 14 . The memory system of claim 9 , wherein the data classification accelerator is configured to divide the deallocated logical range into the set of deallocation zones based on a zone division of a logical space of the non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical range matches the zone division of the logical space of the non-volatile memory device.
15. 15 . The memory system of claim 14 , wherein: the logical space of the non-volatile memory device is divided into a plurality of logical zones; the one or more first deallocation zones are equal to one or more first logical zones from the plurality of logical zones, respectively, such that the one or more first deallocation zones are classified into the one or more aligned zones which are aligned with the one or more first logical zones, respectively; and the one or more second deallocation zones are smaller than one or more second logical zones from the plurality of logical zones, respectively, such that the one or more second deallocation zones are classified into the one or more unaligned zones that are unaligned with the one or more second logical zones, respectively.
16. 16 . The memory system of claim 14 , wherein the non-volatile memory device comprises NAND Flash memory.
17. 17 . A method for operating a memory controller, comprising: receiving a command indicative of a deallocated logical range from a host; dividing the deallocated logical range into a set of deallocation zones, wherein the set of deallocation zones comprises one or more first deallocation zones which are classified into one or more aligned zones, respectively, and one or more second deallocation zones which are classified into one or more unaligned zones, respectively; updating one or more bits of a dataset management (DSM) bitmap that correspond to the one or more aligned zones, respectively, from a first bit value to a second bit value to indicate that the one or more aligned zones are to be deallocated; updating a logical-to-physical (L2P) mapping table based on the one or more unaligned zones to deallocate the one or more unaligned zones; responsive to the updating of the one or more bits of the DSM bitmap and the deallocating of the one or more unaligned zones, generating a response before the one or more aligned zones are deallocated, the response indicating that the deallocated logical range is processed; and sending the response to the host after the one or more unaligned zones are deallocated but before the one or more aligned zones are deallocated.
18. 18 . The method of claim 17 , further comprising updating the L2P mapping table based on the DSM bitmap.
19. 19 . The method of claim 18 , wherein updating the L2P mapping table based on the DSM bitmap comprises: identifying the one or more aligned zones based on the one or more bits of the DSM bitmap; and updating the L2P mapping table based on the one or more aligned zones.
20. 20 . The method of claim 19 , wherein updating the L2P mapping table based on the one or more aligned zones comprises: identifying a first list of logical addresses within the one or more aligned zones; and invalidating the first list of logical addresses in the L2P mapping table.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/CN2023/108308, filed on Jul. 20, 2023, entitled “MEMORY CONTROLLER, MEMORY SYSTEM FOR DATASET MANAGEMENT HANDLING, METHOD, AND STORAGE MEDIUM THEREOF,” which is incorporated herein by reference in its entirety. BACKGROUND The present disclosure relates to memory controller, memory systems, and operation methods thereof. Solid-state drives (SSDs) are a type of non-volatile data storage devices that have gained significant popularity in recent years due to their numerous advantages over traditional hard disk drives (HDDs), such as faster read and write speed, durability and reliability, reduced power consumption, silent operation, and smaller form factors. SSDs typically may use NAND Flash memory for non-volatile storage. Some SSDs, for example enterprise SSDs, also may use volatile memory (e.g., dynamic random-access memory (DRAM)) to enhance their performance, allowing faster access to data and more efficient handling of read and write operations. SUMMARY In one aspect, a memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide a deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones which are classified into one or more aligned zones, respectively. The deallocation accelerator is operatively coupled to the data classification accelerator, and configured to update a dataset management (DSM) bitmap based on the one or more aligned zones. The mapping table accelerator is operatively coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to, responsive to the updating of the DSM bitmap, generate a response indicating that the deallocated logical range is processed. In some implementations, the mapping table accelerator is further configured to update a logical-to-physical (L2P) mapping table based on the DSM bitmap. In some implementations, to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator is further configured to identify the one or more aligned zones from the DSM bitmap, and update the L2P mapping table based on the one or more aligned zones. In some implementations, to update the L2P mapping table based on the one or more aligned zones, the mapping table accelerator is further configured to identify a first list of logical addresses within the one or more aligned zones, and invalidate the first list of logical addresses in the L2P mapping table. In some implementations, the set of deallocation zones further includes one or more second deallocation zones which are classified into one or more unaligned zones, respectively. The mapping table accelerator is further configured to update the L2P mapping table based on the one or more unaligned zones, and generate the response responsive to both the updating of the DSM bitmap and the updating of the L2P mapping table based on the one or more unaligned zones. In some implementations, to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator is further configured to identify a second list of logical addresses within the one or more unaligned zones, and invalidate the second list of logical addresses in the L2P mapping table. In some implementations, the data classification accelerator is configured to divide the deallocated logical range into the set of deallocation zones based on a zone division of a logical space of a non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical range matches the zone division of the logical space of the non-volatile memory device. In some implementations, the logical space of the non-volatile memory device is divided into a plurality of logical zones. The one or more first deallocation zones are equal to one or more first logical zones from the plurality of logical zones, respectively, such that the one or more first deallocation zones are classified into the one or more aligned zones which are aligned with the one or more first logical zones, respectively. The one or more second deallocation zones are smaller than one or more second logical zones from the plurality of logical zones, respectively, such that the one or more second deallocation zones are classified into the one or more unaligned zones which are unaligned with the one or more second logical zones, respectively. In some implementation, the non-volatile memory device includes NAND Flash memory. In another aspect, a memory system includes a non-volatile memory device and a memory controller operatively coupled to the non-volatile memory device. The memory controller is configured to control the non-volatile memory device. The memory controller includes a dat