US-12619549-B2 - System control using sparse data

Abstract

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmit the sparse data pattern.

Inventors

• Michael R. Seningen
• Ben D. Jarrett
• Edward M. McCombs
• Greg M. Hess

Assignees

• APPLE INC.

Dates

Publication Date

20260505

Application Date

20240719

Claims (20)

1. 1 . A method comprising: accessing, by a control circuit of a processor circuit, a set of data stored in a memory circuit of a computer system; identifying, by the control circuit, a number of logical-0 bit values included within the set of data; based on the identifying, determining, by the control circuit, that the set of data satisfies a sparseness condition; based on the determining that the set of data satisfies the sparseness condition, compressing, by the control circuit, the set of data; and storing, by the control circuit, the compressed set of data in the memory circuit.
2. 2 . The method of claim 1 , wherein determining that the set of data satisfies a sparseness condition includes identifying one or more data patterns within the set of data; and wherein storing the compressed set of data in the memory circuit includes omitting, from the compressed set of data, portions of the set of data that match one of the data patterns.
3. 3 . The method of claim 2 , further comprising: receiving, by the control circuit, a read command for a particular location in the memory circuit; and based on determining that the particular location corresponds to an omitted portion of the set of data, halting access to the memory circuit for the particular location.
4. 4 . The method of claim 3 , further comprising completing the read command by returning, by the control circuit, a default value without accessing the memory circuit.
5. 5 . The method of claim 3 , further comprising completing the read command by returning, by the control circuit, a modified version of the omitted portion of the set of data.
6. 6 . The method of claim 5 , wherein returning the modified version of the omitted portion of the set of data includes using an algorithm to generate a compressed version of a portion of the set of data corresponding to the sparseness condition.
7. 7 . The method of claim 1 , determining, by the control circuit, that a given bank of the memory circuit has a threshold level of sparse data; and sending, by the control circuit, a control signal to the memory circuit, wherein the control signal identifies the given bank.
8. 8 . A system comprising: a memory circuit and a control circuit configured to: access a set of data stored in the memory circuit; determine whether ones of the set of data satisfy a sparseness condition; based on a determination that a given data value in the set of data satisfies the sparseness condition, compress the given data value; and storing the compressed data value in the memory circuit.
9. 9 . The system of claim 8 , wherein to determine whether ones of the set of data satisfy the sparseness condition, the control circuit is further configured to identify ones of the set of data that correspond to a particular data pattern; and wherein to store the compressed data value in the memory circuit, the control circuit is further configured to omit, from the compressed data value, at least a portion of bits of the given data value.
10. 10 . The system of claim 8 , wherein the control circuit is further configured to: receive a read command for a particular location in the memory circuit; and based on a determination that the particular location corresponds to a compressed data value, halting access to the memory circuit for the particular location.
11. 11 . The system of claim 10 , wherein to complete the read command, the control circuit is further configured to return a default value without accessing the memory circuit.
12. 12 . The system of claim 10 , wherein to complete the read command, the control circuit is further configured to return a modified version of the given data value.
13. 13 . The system of claim 12 , wherein to return the modified version of the given data value, the control circuit is further configured to generate a compressed version of the given data value.
14. 14 . An apparatus comprising: a memory circuit and a control circuit configured to: access a set of data stored in the memory circuit; based on a number of logical-0 bit values identified within data values in the set of data, determine whether ones of the data values in the set of data satisfy a sparseness condition; based on a determination that a particular number of data values in the set of data satisfy the sparseness condition, compress the set of data; and store the compressed set of data in the memory circuit.
15. 15 . The apparatus of claim 14 , wherein to determine whether ones of the data values in the set of data satisfy the sparseness condition, the control circuit is further configured to identify one or more data patterns within the set of data.
16. 16 . The apparatus of claim 15 , wherein to store the compressed set of data in the memory circuit, the control circuit is further configured to omit, from the compressed set of data, portions of the set of data that match one of the data patterns.
17. 17 . The apparatus of claim 16 , wherein the control circuit is further configured to: receive a read command for a particular location in the memory circuit; and based on a determination that the particular location corresponds to an omitted portion of the set of data, prevent access to the memory circuit for the particular location.
18. 18 . The apparatus of claim 14 , wherein the memory circuit includes a plurality of banks; and wherein the control circuit is further configured to track respective levels of sparse data stored in corresponding ones of the plurality of banks.
19. 19 . The apparatus of claim 18 , wherein the control circuit is further configured to: determine that a particular bank of the plurality of banks has a threshold level of sparse data; and assert a control signal that identifies the particular bank.
20. 20 . The apparatus of claim 19 , wherein the memory circuit is configured to: receive the control signal; and based on the control signal, reduce power to the identified bank.

Description

PRIORITY INFORMATION The present application is a continuation of U.S. application Ser. No. 18/475,890, entitled “System Control Using Sparse Data,” filed Sep. 27, 2023, (now U.S. Pat. No. 12,072,810), which is a continuation of U.S. application Ser. No. 17/662,500, entitled “System Control Using Sparse Data,” filed May 9, 2022 (now U.S. Pat. No. 11,803,480), which is a continuation of U.S. application Ser. No. 16/908,182, entitled “System Control Using Sparse Data,” filed Jun. 22, 2020 (now U.S. Pat. No. 11,327,896), which is a continuation of U.S. application Ser. No. 16/124,166, entitled “System Control Using Sparse Data,” filed Sep. 6, 2018 (now U.S. Pat. No. 10,691,610), which claims priority to U.S. Provisional App. No. 62/564,235, entitled “System Control Using Sparse Data,” filed Sep. 27, 2017, the disclosures of each are incorporated by reference herein in their entireties. BACKGROUND Technical Field The embodiments described herein generally relate to computing systems, and more particularly, to storing and transmitting sparse data. Description of the Relevant Art Computing systems include multiple processors or processor cores that may retrieve and execute program instructions from memory. The program instructions may be part of software programs or applications, and may be designed to perform particular functions, such as word processing, sending and receiving electronic mail, and the like. During execution of such a software program, instructions included in the software program may send data to, or receive data from one or more devices included in, or coupled to, the computing system. Such data may also be stored, and later retrieved from a memory. To facilitate the retrieval of program instructions, and the storage of data, a computing system may include multiple memories. Such memories may vary in storage capacity as well as access time. In some computing systems, memories may be arranged in a hierarchical fashion, with smaller, faster memories coupled directly to processors or processor cores, and larger, slow memory coupled to the processors or processor cores via a memory management unit and a communication or switch fabric. In some computing systems, one or more of the included memories may be disabled when not in use in order to reduce power dissipation of the computing system. To disable such a memory, either a clock signal and/or a power supply signal may be decoupled from the memory. SUMMARY OF THE EMBODIMENTS Various embodiments of a computing system are disclosed. Broadly speaking, an apparatus and a method are contemplated, in which a memory circuit includes a plurality of banks, and a sparse array circuit includes a plurality of entries. A particular entry may correspond to an address location in the memory circuit where a sparse data pattern is stored. The sparse array circuit may receive information indicative of a request to perform a read operation. The request may include an address, which the sparse array circuit may compare to at least one entry of the plurality of entries. The sparse array circuit may, in response to determining that the address matches a particular entry, generate first and second control signals. The memory circuit may disable the read operation based on the first control signal, and a data control circuit may be configured to transmit the sparse data pattern on a bus coupled to the memory based on the second control signal. In one embodiment, the sparse array circuit may be further configured to receive information indicative of a write operation, that includes a second address and write data. The sparse array circuit may be further configured to compare the write data to the sparse data pattern, and in response to a determination that the write data matches the spare data pattern, generate a third control signal and store at least part of the second address in another entry of the plurality of entries. The memory circuit may be further configured to disable the write operation based on the third control signal. In another non-limiting embodiment, to store at least the part of the second address, the spare array circuit may be further configured to map the second address to a particular region of the memory circuit and store third information indicative of a mapping of the second address to the particular region in the another entry. These and other embodiments will become apparent upon reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a generalized block diagram illustrating an embodiment of a memory system. FIG. 2 illustrates a block diagram depicting an embodiment of a memory circuit. FIG. 3 illustrates a block diagram depicting another embodiment of a memory circuit. FIG. 4 illustrates a block diagram of a particular embodiment of a memory circuit. FIG. 5 illustrates a block diagram of a sparse array circuit. FIG. 6 illustrates a block diagram of a non-volatile memory system. FIG. 7 illust